Low-density parity check convolution code (LDPC-CC) encoder and LDPC-CC decoder

ABSTRACT

It is possible to provide and an LDPC-CC (Low-Density Parity-Check Convolution Codes) encoder and an LDPC-CC decoder which performs an error correction encoding and decoding while reducing the amount of a termination sequence required for encoding/decoding the LDPC-CC encoding/decoding and suppressing degradation of the transmission efficiency. The LDPC-CC encoder ( 400 ) includes a weight control unit ( 470 ) which stores a weight pattern ( 475 ) based on an LDPC-CC inspection matrix ( 100 ); and a weight pattern ( 476 ) based on a check matrix ( 300 ) obtained by deforming an LDPC-CC inspection matrix ( 100 ). The weight control unit ( 470 ) controls a weight to be multiplied onto the outputs of a plurality of shift registers ( 410 - 1  to  410 -M,  430 - 1  to  430 -M) by using the weight pattern ( 475 ) when the input bit is an information sequence, and using a weight pattern ( 476 ) which makes a weight value to be multiplied by an inspection bit v 2,t  to be 0 when the input bit is a termination sequence.

TECHNICAL FIELD

The present invention relates to an LDPC-CC (Low-Density Parity-CheckConvolutional Code) encoder, a transmitting apparatus, and an LDPC-CCdecoder, and relates to an LDPC-CC encoder that performs errorcorrection encoding using LDPC-CC, and an LDPC-CC decoder.

BACKGROUND ART

In recent years, attention has been attracted to a Low-DensityParity-Check (LDPC) code as an error correction code that provides higherror correction capability with a feasible circuit scale. Due to itshigh error correction capability and ease of implementation, an LDPCcode has been adopted in an error correction code for IEEE802.11nhigh-speed radio LAN (Local Area Network) systems, digital broadcastingsystems, and so forth.

An LDPC code is an error correction code defined by a low-density paritycheck matrix (that is, a parity check matrix in which there are farfewer 1 elements than 0 elements). An LDPC code is a block code having ablock length equal to number of columns N of a parity check matrix.

However, a characteristic of many current communication systems is thatcommunication is based on variable-length packets and frames, as in thecase of the Ethernet (registered trademark). A problem with applying anLDPC code, which is a block code, to a system of this kind is, forexample, how to make a fixed-length LDPC code block correspond to avariable-length Ethernet (registered trademark) frame. With IEEE802.11n,a wireless LAN standard for which an LDPC code has been adopted,adjustment of the length of a transmission information sequence and anLDPC code block length is performed by applying padding and/orpuncturing to a transmission information sequence. However, a problemwith this is the necessity of changing the coding rate by means ofpadding or puncturing, and of performing redundant sequencetransmission.

In contrast to this kind of block-wise LDPC code (hereinafter referredto as “LDPC-BC: Low-Density Parity-Check Block Code”), an LDPC-CCallowing encoding and decoding of information sequences with arbitrarylength has been investigated (see Non-Patent Document 1).

An LDPC-CC is a convolutional code defined by a low-density parity-checkmatrix.

FIG. 1 shows, as an example, parity check matrix H_([0,n]) ^(T) of anLDPC-CC for which coding rate R=½ (=b/c).

With an LDPC-CC, elements h₁ ^((m))(t) and h₂ ^((m))(t) of parity checkmatrix H_([0,n]) ^(T) are 0 or 1. Also, all elements other than h₁^((m))(t) and h₂ ^((m))(t) included in parity check matrix H_([0,n])^(T) are 0. In FIG. 1, M represents the memory length for an LDPC-CC,and n represents the length of a transmission information sequence. Asshown in FIG. 1, a characteristic of a parity check matrix of an LDPC-CCis that it is a parallelogram-shaped matrix in which 1 is placed only indiagonal terms of the matrix and neighboring elements, and thebottom-left and top-right elements of the matrix are zero.

Here, if an example in which coding rate R=½ (=b/c) is shown, when h₁⁽⁰⁾(t)=1 and h₂ ⁽⁰⁾(t)=1, LDPC-CC encoding is performed by means ofEquation (1) and Equation (2) in accordance with parity check matrixH_([0,n]) ^(T) in FIG. 1.

$\begin{matrix}\left( {{Equation}\mspace{14mu} 1} \right) & \; \\{v_{1,t} = u_{t}} & \lbrack 1\rbrack \\\left( {{Equation}\mspace{14mu} 2} \right) & \; \\{v_{2,t} = {{\sum\limits_{i = 0}^{M}{{h_{1}^{(i)}(t)}u_{t - i}}} + {\sum\limits_{i = 1}^{M}{{h_{2}^{(i)}(t)}v_{2,{t - i}}}}}} & \lbrack 2\rbrack\end{matrix}$

Here, u_(t) represents a transmission information sequence, and v_(1,t)and v_(2,t) represent transmission codeword sequences.

FIG. 2 shows an example of a main configuration of an LDPC-CC encoderthat executes Equation (1) and Equation (2). As shown in FIG. 2, LDPC-CCencoder 10 comprises shift registers 11-1 through 11-M and 14-1 through14-M, weight multipliers 12-0 through 12-M and 13-0 through 13-M, modulo2 adder (exclusive OR computing element) 15, bit counter 16, and weightcontrol section 17.

Shift registers 11-1 through 11-M and 14-1 through 14-M are registersstoring and v_(1,t-i) and v_(2,t-i) (where i=0, . . . , M) respectively,and at a timing at which the next input comes in, send a stored value tothe adjacent shift register to the right, and store a new value sentfrom the adjacent shift register to the left.

Weight multipliers 12-0 through 12-M and 13-0 through 13-M switch aweight value to 0 or 1 in accordance with a control signal output fromweight control section 17. Based on a count output from bit counter 16and a weight pattern conforming to a parity check matrix stored inweight control section 17, weight control section 17 sends the values ofh₁ ^((m))(t) and h₂ ^((m))(t) at that timing to weight multipliers 12-0through 12-M and 13-0 through 13-M. Modulo 2 adder 15 performs modulo 2addition on the outputs of weight multipliers 12-0 through 12-M and 13-0through 13-M, and calculates v_(2,t). Bit counter 16 counts the numberof bits of an input transmission information sequence.

By employing this kind of configuration, LDPC-CC encoder 10 can performLDPC-CC encoding in accordance with a parity check matrix.

A characteristic of an LDPC-CC encoder is that it can be implementedwith extremely simple circuitry as compared with the circuitry of anencoder that performs generator matrix multiplication, or an LDPC-BCencoder that performs computation based on backward substitution orforward substitution. Also, since an LDPC-CC is a convolutional code, itis not necessary to divide a transmission information sequence intofixed-length blocks when encoding, and an information sequence of anylength can be encoded.

In LDPC-CC decoding, a sum-product algorithm can be applied based on aparity check matrix in the same way as with an LDPC-BC. Therefore, it isnot necessary to use a BCJR (Bahl, Cocke, Jeinek, Raviv) algorithm, or adecoding algorithm based on maximum likelihood sequence estimation suchas a Viterbi algorithm, and decoding processing can be completed withlittle processing delay. Furthermore, in Non-Patent Document 1, apipeline-based decoding algorithm is proposed that takes advantage ofthe structure of the parity check matrix, in which 1s are arranged in aparallelogram configuration.

When LDPC-CC and LDPC-BC decoding characteristics are compared usingparameters such that the decoder circuit scales are equivalent, LDPC-CCdecoding characteristics are shown to be superior (see Non-PatentDocument 1).

Now we consider that a encoder terminate LDPC-CC encoding at anarbitrary length n, and a decoder decodes a corresponding receivedcodeword sequence. In this case, the decoder requires the codeword thatencoded transmission information sequences after n-th bit and shiftregister states at the end of encoding in order to make probabilitypropagation of the rear 2M bits equivalent to that of the other bits insum-product decoding.

However, when a transmission information sequence is simply encoded,since encoder shift register states at the end of encoding depend on thetransmission information sequence, it is difficult to decide thosestates uniquely at a receiver side.

If decoding processing is performed on the receiver side based on areceived codeword sequence in such a situation, a phenomenon occurswhereby errors increase at the end of a received information sequenceobtained after decoding, particularly in the rear 2M bits.

In order to prevent such errors, it is necessary for terminatingprocessing (termination) that uniquely decides a terminal state ofencoding to be executed on a transmission information sequence.

With a convolutional code conforming to IEEE802.11n, termination isexecuted by adding “tail bits” comprising the six 0s to the rear of atransmission information sequence when performing encoding. The lengthof tail bits, six, is the same number as shift registers in an encoder.By so doing, the state of an encoder shift registers can be madeall-zeros at a point in time at which tail bit input ends. A codewordoutput when a tail bit is input is necessary for decoding processing onthe receiver side, and is therefore transmitted to the receiver sidetogether with a transmission codeword.

In the case of an LDPC-CC, as shown in Equation (1), codewords v_(2,t-i)for the past M times are necessary to find codeword v_(2,t), andtherefore shift registers for storing codeword v_(2,t−i) for the past Mtimes are provided in an LDPC-CC encoder. A register storing atransmission information sequence can be set to an all-zero state bymaking the end of a transmission information sequence a length-Mall-zero sequence (termination), but a problem is that it is difficultto set a shift register storing codeword v_(2,t-i) to an all-zero statewith only this termination processing.

In Non-Patent Document 2, termination processing is proposed that setsthe state of a shift register at the end of encoding to all-zeros byperforming encoding after adding a termination sequence to the rear of atransmission information sequence.

In the termination processing proposed in Non-Patent Document 2, atransmission codeword sequence is defined as shown in Equation (3).

Equation (3) is an example for a case in which coding rate R=½. InEquation (3), v_(1×2) is a length-2n codeword sequence obtained byconvolutional encoding of a length-n information sequence, x_(1×2L) is atermination codeword sequence obtained by convolutional encoding of alength-L termination sequence, and 0_(1×2M) is a length-2M 0-sequence.

[3][v _(1×2n) ,x _(1×2)L,0_(1×2M)]H′_(2(n+L+M)×(n+L+M))=0_(1×(n+L+M) . . .)   (Equation 3)

Here, termination sequence x_(1×2L) is decided by Equation (4) andEquation (5).

$\begin{matrix}\left( {{Equation}\mspace{14mu} 4} \right) & \; \\{{\left\lbrack {v_{1 \times 2n},x_{1 \times 2L},0_{1 \times 2M}} \right\rbrack\begin{bmatrix}A_{2n \times n} & B_{2n \times {({L + M})}} \\0_{2L \times n} & D_{2L \times {({L + M})}} \\0_{2M \times n} & F_{2M \times {({L + M})}}\end{bmatrix}} = 0_{1 \times {({n + L + M})}}} & \lbrack 4\rbrack \\\left( {{Equation}\mspace{14mu} 5} \right) & \; \\{{x_{1 \times 2L}D_{2L \times {({L + M})}}} = {{v_{1 \times 2n}B_{2n \times {({L + M})}}} = \beta}} & \lbrack 5\rbrack\end{matrix}$

The state of a shift register can be set to an all-zero state byencoding a transmission codeword sequence to which such a terminationsequence has been added with an LDPC-CC encoder. By having atransceiver-side communication apparatus transmit a transmissioncodeword that has undergone termination processing in this way to thereceiver side, the receiver side decoder can uniquely decide a shiftregister state at the end of encoding, and performs error correctiondecoding at a desired level of performance.

-   Non-Patent Document 1: Alberto Jimenez Felstorom, and Kamil Sh.    Zigangirov, “Time-Varying Periodic Convolutional Codes With    Low-Density Parity-Check Matrix.”, IEEE Transactions on Information    Theory, Vol. 45, No. 6, pp. 2181-2191, September, 1999.-   Non-Patent Document 2: Zhengang Chen, Stephen Bates, and Ziaodai    Dong, “Low-Density Parity-Cheek Convolutional Codes Applied to    Packet Based Communication Systems”, Proceeding of IEEE Globecom    2005, pp. 1250-1254.-   Non-Patent Document 3: Stephen Bates, Duncan G. Elliott, and    Ramkrishna Swamy, “Termination Sequence Generation Circuits for    Low-Density Parity-Check Convolutional Codes,” IEEE Transaction on    Circuits and Systems-I: Regular Papers, vol. 53, no. 9, pp.    1909-1917, September 2006-   Non-Patent Document 4: S. Lin, D. J. Jr., Costello, “Error control    coding: Fundamentals and applications,”,582-598, Prentice-Hall.-   Non-Patent Document 5: R. M. Tanner, D. Sridhara, A.    Sridharan, T. E. Fuja, and D. J. Costello Jr., “LDPC block and    convolutional codes based on circulant matrices,” IEEE Trans.    Inform. Theory, vol. 50, no. 12, pp. 2966-2984, December 2004.-   Non-Patent Document 6: G. Richter, M. Kaupper, and K. Sh.    Zigangirov, “Irregular low-density parity-Check convolutional codes    based on protographs,” Proceeding of IEEE ISIT 2006, pp 1633-1637.-   Non-Patent Document 7: A. Pusane, R. Smarandache, P. Vontobel,    and D. J. Costello Jr., “On deriving good LDPC convolutional codes    from QC LDPC block codes,” Proc. of IEEE ISIT 2007, pp. 1221-1225,    June 2007.-   Non-Patent Document 8: Howard H. MA and Jack K. Wolf, On “Tail Bitin    Convolutional Codes”, IEEE Transactions on communications, vol.    COM-34, No. 2, pp. 104-111, February 1986

DISCLOSURE OF INVENTION Problems to be Solved by the Invention

However, with the above conventional configuration, a 2L-bit sequence(where L≧M) is necessary as a transmitted termination sequence, andthere are problems of an increase in the amount of overhead anddegradation of transmission efficiency resulting from sending aredundant signal sequence. For example, when an 8,000-bit transmissioninformation sequence is transmitted using an LDPC-CC with memory lengthM=200, 400 bits or more—that is, redundant bits equivalent to 5% or moreof the transmission information sequence—must be transmitted fortermination. Also, transmission efficiency degradation due totermination sequence transmission is more pronounced when thetransmission information sequence length is short, when the coding rateis high, or when memory length M is large.

It is an object of the present invention to provide an LDPC-CC encoderand LDPC-CC decoder that enable error correction encoding and decodingto be performed while reducing the amount of a termination sequencenecessary for LDPC-CC encoding/decoding and suppressing degradation oftransmission efficiency.

Means for Solving the Problem

An LDPC-CC encoder of the present invention employs a configurationhaving: a plurality of shift registers; a plurality of weightmultiplication sections that multiply outputs of the shift registers bya weight; an exclusive OR computing element that finds an exclusive ORof outputs of the plurality of weight multiplication sections; a bitcounter that counts a number of input bits that are encoded; and aweight control section that controls weights of the plurality of weightmultiplication sections according to the number of bits.

One aspect of an LDPC-CC encoder of the present invention employs aconfiguration in which the weight control section stores a first weightpattern conforming to a parity check matrix of an LDPC-CC and a secondweight pattern conforming to a parity check matrix obtained by thedeformed parity check matrix, and uses the first weight pattern when theinput bits are an information sequence, and uses the second weightpattern when the input bits are a termination sequence.

According to this configuration, LDPC-CC encoding that uses a paritycheck matrix of an LDPC-CC can be performed. Also, a shift registerweight value can be switched according to whether input bits are aninformation sequence or a termination sequence. Therefore when inputbits are a termination sequence, LDPC-CC encoder can concludetermination processing using weight values for a transmission codewordsequence which are set to be 0 irrespective of the value of thetransmission codeword sequence. As a result, the length of a transmittedtermination sequence can be reduced.

Advantageous Effects Of Invention

The present invention enables error correction encoding and decoding tobe performed while reducing the amount of a termination sequencenecessary for LDPC-CC encoding/decoding and suppressing degradation oftransmission efficiency.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a drawing showing an example of a conventional parity checkmatrix of LDPC-CC;

FIG. 2 is a drawing showing an example of a main configuration of aconventional LDPC-CC encoder;

FIG. 3 is a drawing showing an example of a parity check matrix of anLDPC-CC when a conventional termination sequence has been added;

FIG. 4 is a drawing showing an example of a parity check matrix of anLDPC-CC when a conventional termination sequence is not added;

FIG. 5 is a drawing showing an example of a parity check matrixaccording to Embodiment 1 of the present invention;

FIG. 6 is a block diagram showing a configuration of an LDPC-CC encoderaccording to Embodiment 1;

FIG. 7 is a block diagram showing a configuration of a weight controlsection according to Embodiment 1;

FIG. 8 is a drawing showing another example of a parity check matrixaccording to Embodiment 1;

FIG. 9 is a drawing showing an example of a parity check matrixaccording to Embodiment 2 of the present invention;

FIG. 10 is a block diagram showing a configuration of an LDPC-CC encoderaccording to Embodiment 2;

FIG. 11 is a block diagram showing a configuration of a weight controlsection according to Embodiment 2;

FIG. 12 is a drawing showing an example of a parity check matrixaccording to Embodiment 3 of the present invention;

FIG. 13 is a block diagram showing a configuration of an LDPC-CC encoderaccording to Embodiment 3;

FIG. 14 is a block diagram showing a main configuration of atransmitting apparatus according to Embodiment 4 of the presentinvention;

FIG. 15 is a drawing for explaining an example of puncturing accordingto Embodiment 4;

FIG. 16 is a block diagram showing a main configuration of atransmitting apparatus according to Embodiment 5 of the presentinvention;

FIG. 17 is a block diagram showing a main configuration of a receivingapparatus according to Embodiment 5;

FIG. 18 is a block diagram showing another main configuration of atransmitting apparatus according to Embodiment 5;

FIG. 19 is a block diagram showing a main configuration of atransmitting apparatus according to Embodiment 6 of the presentinvention;

FIG. 20 is a block diagram showing a main configuration of a receivingapparatus according to Embodiment 6;

FIG. 21 is a block diagram showing another main configuration of areceiving apparatus according to Embodiment 6;

FIG. 22 is a drawing showing a configuration of a parity check matrix ofan LDPC-CC according to Embodiment 7;

FIG. 23 is a drawing for explaining a general puncturing method;

FIG. 24 is a drawing showing the correspondence between transmissioncodeword sequence v and parity check matrix H according to a generalpuncturing method;

FIG. 25 is a drawing for explaining a puncturing method according toEmbodiment 7;

FIG. 26 is a drawing showing the correspondence between transmissioncodeword sequence v and parity check matrix H according to a puncturingmethod according to Embodiment 7;

FIG. 27 is a block diagram showing another main configuration of atransmitting apparatus according to Embodiment 7;

FIG. 28 is a drawing showing an example of a puncture pattern accordingto Embodiment 7;

FIG. 29 is a drawing showing another puncture pattern according toEmbodiment 7;

FIG. 30 is a drawing showing another puncture pattern according toEmbodiment 7;

FIG. 31 is a drawing showing another puncture pattern according toEmbodiment 7;

FIG. 32 is a drawing showing another puncture pattern according toEmbodiment 7;

FIG. 33 is a drawing for explaining decoding processing timing;

FIG. 34 is a drawing showing an example of a parity check matrixaccording to Embodiment 8 of the present invention;

FIG. 35 is a block diagram showing a configuration of an LDPC-CC encoderaccording to Embodiment 8;

FIG. 36 is a block diagram showing a configuration of a weight controlsection according to Embodiment 8;

FIG. 37 is a drawing showing an example of a parity check matrixaccording to Embodiment 9 of the present invention;

FIG. 38 is a block diagram showing a configuration of a transmittingapparatus according to Embodiment 9;

FIG. 39 is a block diagram showing a configuration of a polynomialadjustment section according to Embodiment 9;

FIG. 40 is a block diagram showing another configuration of a polynomialadjustment section according to Embodiment 9;

FIG. 41 is a block diagram showing a configuration of a receivingapparatus according to Embodiment 10 of the present invention;

FIG. 42 is a block diagram showing a configuration of a sum-productdecoding section according to Embodiment 10;

FIG. 43 is a block diagram showing a configuration of a row processingcomputation section according to Embodiment 10; and

FIG. 44 is a block diagram showing a configuration of a columnprocessing computation section according to Embodiment 10.

BEST MODE FOR CARRYING OUT THE INVENTION

Now, embodiments of the present invention will be described in detailwith reference to the accompanying drawings.

(Embodiment 1)

In this embodiment, descriptions are given of a parity check matrix anda configuration of an encoder that performs LDPC-CC encoding using thatparity check matrix. The parity check matrix described in thisembodiment is that matrix elements corresponding to the rear M bits of atransmission information sequence have been deformed from the paritycheck matrix in order to reduce the number of termination sequences.

FIG. 3 shows an example of a parity check matrix of an LDPC-CC. Paritycheck matrix 100 in FIG. 3 is an example of a case with memory lengthM=5, coding rate 1/2, and transmission information sequence length n.For the sake of simplicity, FIG. 3 shows only a part corresponding tothe end part of a transmission codeword sequence, and the followingtermination sequence, extracted from parity check matrix 100.

In parity check matrix 100, rows correspond to bits of a transmissioncodeword sequence, termination sequence, and zero sequence. Also,columns p₁, p₂, p₁₈ correspond to parity check equations. To simplifythe description, indexes are assigned in order from the right-handcolumn. The LDPC-CC encoding is performed so that, in each column, amodulo 2 addition result (exclusive OR operation result) of transmissioncodeword bits corresponding to a row in which a 1 is placed becomeszero. Parity check matrix 100 in FIG. 3 is an example of a systematiccode in which transmission information sequence u_(t) is includeddirectly in that form in transmission codeword sequences v_(1,t) andv_(2,t), and transmission codeword bits v_(1,t) and v_(2,t) arerepresented by Equation (1).

Here, the reason why termination is necessary will be explained. Iftermination is not performed—that is, if a parity check matrix isterminated with a v_(2,t), row—the parity check matrix becomes as shownin FIG. 4. Consider a case in which sum-product decoding is performed onthe receiver side using parity check matrix 200 in FIG. 4. Insum-product decoding, a repetition code decoding and a single paritycheck code decoding are iteratively performed. The repetition codedecoding is performed by logarithmic likelihood ratio additionprocessing in the parity check matrix 200 row direction. The decoding ofa single parity check code is performed by multiplication processing ofvalues of hyperbolic tangent of logarithmic likelihood ratio in thecolumn direction. At this time, to consider the v_(2,n) row of paritycheck matrix 200, there is only one column (p₁) in which a 1 is placedin the v_(2,n) row. The same also applies to the v_(1,n), v_(1,n−1),v_(2,n−1), v_(2,n−2), v_(2,n−3), and v_(2,n−4) rows. With such rows,sufficient coding gain by the repetition code cannot be obtained, andtherefore these codeword bits also adversely affect the decodingperformance of other codeword bits. As a result, many bit errors occurin the rear part of a post-decoding received information sequence.

In contrast to this, when a termination sequence and zero sequence areadded after transmission codeword sequences v_(1,n) and v_(2,n),sufficient encoding gain can be obtained when iterative decoding isperformed on transmission codeword sequences v_(1,n) and v_(2,n).Because there is present in the v_(2,n) row in parity check matrix 100 acolumn in which the same number of 1s are placed as in another v_(2,x)row, as shown in FIG. 3.

Furthermore, sufficient encoding gain can also be obtained for codewordbits other than v_(2,n) included in parity check equations (p₆, p₁₁)including codeword bit v_(2,n) by adding a termination sequence and zerosequence. Therefore bit errors no longer occur in the rear part of apost-decoding received information sequence. However, in this ease, itis necessary to transmit a 2L-bit (in this example, 2M=10-bit)termination sequence in addition to a 2n-bit transmission codewordsequence, and degradation of transmission efficiency is a problem.

Thus, in this embodiment, LDPC-CC encoding is performed using a paritycheck matrix obtained by deforming matrix elements corresponding to therearmost M bits of a transmission information sequence in parity checkmatrix 100. This is described in detail below.

FIG. 5 shows parity check matrix 300 according to this embodiment.Parity check matrix 300 in FIG. 5 has a I placed in a row correspondingto v_(2,t) in parity check equation (p₆, p₇, p₈, p₉, p₁₀) columns usedfor encoding of x_(2,1), x_(2,2), x_(2,3), x_(2,4), and x_(2,5) changedto a 0 with respect to parity check matrix 100 in FIG. 3. Specifically,parity check matrix 300 is a matrix obtained by changing a rightmost 1in rows corresponding to v_(2,n), v_(2,n−1), v_(2,n−2), v_(2,n−3), andv_(2,n−4) of parity check matrix 100 to a 0. Rows relating totransmission codeword bits prior to v_(2,n−5) of parity check matrix 300are the same as in parity check matrix 100.

In parity check matrix 300, since the rightmost value in rowscorresponding to v_(2,n), v_(2,n−1), v_(2,n−2), v_(2,n−3), and v_(2,n−4)is a 0, when this parity check matrix 300 is used, the value of v_(2,t)is unnecessary for encoding of x_(2,1), x_(2,2), x_(2,3), x_(2,4), andx_(2,5), and only transmission information sequence v_(1,t) (=u_(t)) andx_(1,x) are necessary. Consequently, it is not necessary for v_(1,t) andv₂,t shift registers both to be set to an all-zero state, and only thev_(1,t) shift register need be set to an all-zero state. The v_(1,t)shift register can be set to an all-zero state by input of x_(1,1),x_(1,2), x_(1,3), x_(1,4), and x_(1,5) to the encoder as all-zeros, inthe conventional way.

Furthermore, if it is decided beforehand on the transmitting side andreceiver side that x_(1,1) through x_(1,5) are to be set to all-zeros,it is not necessary for x_(1,1) through x_(1,5) to actually betransmitted to the receiver, and only x_(2,m) obtained by encoding needbe transmitted. At this time, the receiver performs decoding with aLog-Likelihood Ratio (LLR) of a bit corresponding to x_(1,m) as ∞(infinity).

In this way, a transmitted termination sequence can be reduced to M bitsat least from the conventional 2L bits.

For example, when parity check matrix 300 is used, if the 3 bitsx_(2,1), x_(2,2), and x_(2,3) are transmitted, codeword bits for allparity check equations relating to v_(1,t) and v_(2,t) can be obtainedon the receiver side. By contrast, when parity check matrix 100 is used,it is necessary for 10-bit termination sequence x_(1,1) through x_(1,5),x_(2,1) through x_(2,5) to be transmitted. That is to say, when paritycheck matrix 300 is used, the termination sequence transmission amountcan be reduced by 30% compared with a case in which parity check matrix100 is used.

A configuration of an LDPC-CC encoder that performs LDPC-CC encodingusing parity check matrix 300 in FIG. 5 will now be described withreference to the accompanying drawings.

FIG. 6 is a block diagram showing a main configuration of an LDPC-CCencoder according to this embodiment.

In FIG. 6, LDPC-CC encoder 400 comprises shift registers 410-1 through410-M and 440-1 through 440-M, weight multipliers 420-0 through 420-Mand 430-0 through 430-M, modulo 2 adder (exclusive logical sum computingelement) 450, bit counter 460, weight control section 470, andpuncturing section 480.

Shift registers 410-1 through 410-M and 440-1 through 440-M areregisters storing v_(2,t−i) and v_(2,t−i) (where i=0, . . . , M)respectively, and at a timing at which the next input comes in, send astored value to the adjacent shift register to the right, and store anew value sent from the adjacent shift register to the left. Here, nrepresents the transmission information sequence length of transmissioninformation sequence u_(t).

Weight multipliers 420-0 through 420-M and 430-0 through 430-M switch aweight value to 0 or 1 in accordance with a control signal output fromweight control section 470.

Modulo 2 adder 450 performs modulo 2 addition on the outputs of weightmultipliers 420-0 through 420-M and 430-0 through 430-M, and calculatesv_(2,t).

Bit counter 460 counts the number of bits of an input transmissioninformation sequence and termination sequence, and outputs the bit countto weight control section 470.

Based on the bit count output from bit counter 460 and a weight patternconforming to parity check matrix 300 stored in weight control section470, weight control section 470 sends the values of parity check matrixelements h₁ ^((m))(t) and h₂ ^((m))(t) at that timing to weightmultipliers 420-0 through 420-M and 430-0 through 430-M.

FIG. 7 is a configuration diagram of weight control section 470. Weightcontrol section 470 comprises selectors 471 and 474, weight patternstorage section 472, and weight pattern storage section 473.

Selector 471 has a bit count and transmission information sequencelength n as input, and if bit count≦transmission information sequencelength n, sends the bit count to weight pattern storage section 472. Onthe other hand, if bit count>transmission information sequence length n,selector 471 sends the bit count to weight pattern storage section 473.

Weight pattern storage section 472 stores the weight pattern indicatedby weight pattern 475, and outputs h_(a1), h_(a2), h_(a3), and h_(a4) toselector 474 periodically as the bit count increases. Weight pattern 475comprises parity check matrix 100 matrix elements h_(1(m))(t) and h₂^((m))(t) (where m=0, . . . , M).

Weight pattern storage section 473 stores the weight pattern indicatedby weight pattern 476, and outputs h_(b1), h_(b2), h_(b3), and h_(b4) toselector 474 periodically as the bit count increases. Weight pattern 476comprises matrix elements h_(1(m))(t) and h₂ ^((m))(t) (where m=0, . . ., M) of parity check matrix 300 obtained by deforming parity checkmatrix 100 elements.

Selector 474 outputs matrix elements h_(a1), h_(a2), h_(a3), and h_(a4)input from weight pattern storage section 472 or matrix elements h_(b1),h_(b2), h_(b3), and h_(b4) input from weight pattern storage section473, to weight multipliers 420-0 through 420-M and 430-0 through 430-M.

That is to say, when input bits are a transmission information sequenceaccording to the result of a comparison between a bit count andtransmission information sequence length in conjunction with selector471, selector 474 outputs matrix elements of weight pattern 475conforming to parity check matrix 100 stored in weight pattern storagesection 472 to weight multipliers 420-0 through 420-M and 430-0 through430-M. On the other hand, when input bits are a termination sequence,selector 474 outputs matrix elements of weight pattern 476 conforming toparity check matrix 300 obtained by deforming parity check matrix 100stored in weight pattern storage section 473 to weight multipliers 420-0through 420-M and 430-0 through 430-M.

Puncturing section 480 punctures termination sequence x_(1,1) throughx_(1,L) from transmission codeword sequences v_(1,1) through v_(1,n) andx_(1,1) through x_(1,L).

The operation of LDPC-CC encoder 400 configured as described above willnow be explained.

Transmission information sequence u₁ through u_(n) and terminationsequence x_(1,1) through x_(1,L) are output sequentially to shiftregister 410-1, weight multiplier 420-0, and bit counter 460, andtransmission information sequence u_(t) is output to puncturing section480 as transmission codeword sequence v_(2,t).

Bit counter 460 counts the number of bits of input transmissioninformation sequence u₁ through u_(n) and termination sequence x_(1,1)through x_(1,L), and outputs the obtained bit count to weight controlsection 470.

Weight control section 470 selects either weight pattern 475 or weightpattern 476 according to the result of a comparison between the bitcount and transmission information sequence length n, and outputs matrixelements of the selected weight pattern to weight multipliers 420-0through 420-M and 430-0 through 430-M.

Specifically, if bit count≦transmission information sequence length—thatis, the input bits are a transmission information sequence—matrixelements of weight pattern 475 conforming to parity check matrix 100 areoutput to weight multipliers 420-0 through 420-M and 430-0 through430-M. Weight pattern 475 is identical to a pattern used in conventionalLDPC-CC encoding in which 1 is placed at the rightmost end of TOWScorresponding to v_(2,n), v_(2,n−1), v_(2,n−2), v_(2,n−3), andv_(2,n−4).

On the other hand, if bit count>transmission information sequencelength—that is, the input bits are a termination sequence—a weightpattern 476 parity check matrix conforming to parity check matrix 300obtained by deforming parity check matrix 100 is output to weightmultipliers 420-0 through 420-M and 430-0 through 430-M. Weight pattern476 is a pattern in which a 1 placed at the rightmost end of rowscorresponding to v_(2,n), v_(2,n−1), v_(2,n−2), v_(2,n−3), and v_(2,n−4)has been changed to a 0 with respect to weight pattern 475. That is tosay, this is a pattern in which rightmost h₂ ⁽⁵⁾ of a parity checkmatrix row is 0 in FIG. 7. In the example of parity cheek matrix 100, h₂⁽¹⁾ through h₂ ⁽⁴⁾ are 0, and therefore, by using weight pattern 476,when a termination sequence is input the weight value by which v_(2,n),v_(2,n−1), v_(2,n−2), v_(2,n−3), and v_(2,n−4) are multiplied becomes 0,and v_(2,n), v_(2,n−1), v_(2,n−2), v_(2,n−3), and v_(2,n−4) are nolonger used in encoding of x_(2,1), x_(2,2), x_(2,3), x_(2,4), andx_(2,5). As a result, it is no longer necessary for shift registers440-0 through 440-M relating to v_(2,t) to be made 0 at the end ofencoding, and redundant bits for making v_(2,t) 0 are unnecessary.

Furthermore, puncturing section 480 punctures termination sequencex_(1,1) through x_(1,L) from transmission codeword sequences v_(1,1)through and x_(1,1) through x_(1,L). As a result, degradation oftransmission efficiency due to termination sequence transmission can bereduced compared with a conventional method.

As described above, in this embodiment it has been assumed that LDPC-CCencoder 400 is equipped with plurality of shift registers 410-1 through410-M and 440-1 through 440-M, plurality of weight multipliers 420-0through 420-M that multiply outputs of shift registers 410-1 through410-M and 440-1 through 440-M by a weight, modulo 2 adder 450 thatperforms modulo 2 addition of outputs of weight multipliers 420-0through 420-M, bit counter 460 that counts a number of input bits thatare encoded, and weight control section 470 that controls weights ofweight multipliers 420-0 through 420-M according to the number of inputbits. By this means, LDPC-CC encoding that uses an LDPC-CC parity checkmatrix can be performed.

Also, it has been assumed that weight control section 470 stores weightpattern 475 conforming to LDPC-CC parity check matrix 100 and weightpattern 476 conforming to parity check matrix 300 obtained by deformingLDPC-CC parity check matrix 100, and uses weight pattern 475 when inputbits are an information sequence, and uses weight pattern 476 when inputbits are a termination sequence. By this means, transmission codewordsequences v_(1,t) and v_(2,t) can be acquired by using weight pattern475 when transmission information sequence u_(t) is input, andtransmission codeword sequences v_(1,t) and v_(2,t) can be acquired byusing weight pattern 476 in which the weight value by which v_(2,t) ismultiplied is made 0 when termination sequence x_(1,m) is input, therebyenabling a transmitted termination sequence to be reduced.

Furthermore, by providing puncturing section 480 that punctures a zerosequence (x_(1,1) through x_(1,L)) known by the transceiver side and thereceiver side that is transmitted for termination, a decrease intransmission efficiency due to termination sequence transmission can besuppressed.

Whereas with a termination method disclosed in Non-Patent Document 2separate circuitry is necessary in order to find termination sequencex_(1×2L) (see Non-Patent Document 3), this embodiment enables encodingprocessing including termination to be completed without the need forsuch special circuitry.

(Sample Variant)

FIG. 8 is a drawing showing another example of a parity check matrixaccording to this embodiment. In parity check matrix 500 in FIG. 8, a 1placed in the rightmost position of a row corresponding to v_(2,1) inparity check equations (p₆, p₇, p₈, p₉, p₁₀) used for encoding ofx_(2,1), x_(2,2), x_(2,3), x_(2,4), and x_(2,5) is changed to a 0, andfurthermore a 1 is newly placed in a column other than a parity checkequation (p₆, p₇, p₈, p₉, p₁₀) used for encoding of x_(2,1), x_(2,2),x_(2,3), x_(2,4), and x_(2,5) in rows corresponding to v_(2,n),v_(2,n−1), v_(2,n−2), v_(2,n−3), and v_(2,n−4). As shown by the arrowsin FIG. 8, positions at which a 1 is placed are shifted to a columnother than a parity check equation (p₆, p₇, p₈, p₉, p₁₀) used forencoding of x_(2,1), x_(2,2), x_(2,3), x_(2,4), and x_(2,5).

In this way, in addition to obtaining the same kind of effect as withparity check matrix 300 in at least halving a transmitted terminationsequence to L bits from the conventional 2L bits, parity check matrix500 enables encoding gain due to repetition code decoding processing insum-product decoding to be maintained since the number of row-direction1s (row weight) does not change in a row in which a position at which a1 is placed is shifted.

Also, although parity check matrix 500 in FIG. 8 illustrates an examplein which the number of 1s shifted to the left is not the same for eachrow, parity check matrix 500 is not limited to this, and provision mayalso be made for the same number of 1s to be shifted to the left in eachrow. When the number of 1s shifted to the left is the same for each row,fewer kinds of weight patterns need to be stored by weight controlsection 470 than when the number of 1s shifted to the left is not thesame for each row.

The effect of the present invention of suppressing degradation oftransmission efficiency through a reduction in the amount of atermination sequence can also be obtained if all is relating to encodingof x_(2,1), x_(2,2), x_(2,3), x_(2,4), and x_(2,5) are shifted, or ifonly 1s of some rows are shifted and is of other rows are only changedto 0 or the like.

(Embodiment 2)

In this embodiment, descriptions are given of a parity check matrix thatis designed so that memory length M of LDPC-CC decreases toward the rearof a transmission information sequence in order to reduce the number oftermination sequence, and a configuration of an LDPC-CC encoder that isbased on that parity check matrix.

FIG. 9 shows an example of a parity check matrix according to thisembodiment. Parity cheek matrix 600 in FIG. 9 is an example of a casewith coding rate R=b/c=½ and transmission information sequence length n.Parity check matrix 600 differs from parity check matrix 100 in FIG. 3that memory length M decreases from 5 to 4 to 3 successively as theindex of transmission information sequence u_(t) approaches n.

That is to say, as shown in FIG. 9, when parity check matrix 600 is usedencoding is performed for transmission information sequence u_(i)through u_(n−4) with memory length M=5, and transmission codewordsequences v_(1,1) through v_(1,n−4) and v_(2,1) through v_(2,n−4) areacquired. For transmission information sequence u_(n−3) through u_(n−1),encoding is performed with memory length M=4, and transmission codewordsequences through v_(1,n−1) and v_(2,n−3) through v_(2,n−1) areacquired. And for transmission information sequence u_(n) andtermination sequence x_(1,1) through x_(1,3), encoding is performed withmemory length M=3, and v_(1,n), v_(2,n) and x_(1,1) through x_(1,3),x_(2,1) through x_(2,3) are acquired.

As explained above, it is necessary for termination sequence length L tosatisfied the relationship L≧M. Therefore, if encoder memory length M issmall at a point in time at which termination is performed, terminationsequence length L can be made correspondingly shorter.

Thus, by performing LDPC-CC encoding using parity check matrix 600 shownin FIG. 9, the length of a termination sequence can be made shorter thanheretofore, and as a result, degradation of transmission efficiency dueto termination sequence transmission can be suppressed.

A characteristic of an LDPC-CC is that greater encoding gain and abetter error rate characteristic are obtained the larger the value ofmemory length M. Consequently, if memory length M is reduced toward therear of a transmission codeword sequence, as in the case of parity checkmatrix 600, the bit error rate of the rear part can be expected todegrade. However, a characteristic of an LDPC-CC is that, since a shiftregister state at the end of encoding is decided as an all-zero state byperforming appropriate termination processing, and LLRs of zero sequencewhich follows a termination sequence can be set to infinity at the timeof decoding, the bit error rate of the rear part of a informationsequence is better than that of other parts.

Consequently, when LDPC-CC encoding using parity check matrix 600 whosememory length M is reduced toward the rear of a transmission codewordsequence is performed, a problem of degradation of the bit error rate ofthe rear part of a information sequence does not arise.

Next, we describe a configuration of an LDPC-CC encoder that performsLDPC-CC encoding using parity check matrix 600 in FIG. 9 with referenceto the accompanying drawings.

FIG. 10 is a block diagram showing a main configuration of an LDPC-CCencoder according to this embodiment. In the description of thisembodiment, configuration parts identical to those in FIG. 6 areassigned the same reference numbers as in FIG. 6, and descriptionsthereof are omitted. As compared with LDPC-CC encoder 400 in FIG. 6,LDPC-CC encoder 700 in FIG. 10 does not have puncturing section 480 andis equipped with weight control section 710 instead of weight controlsection 470.

Based on a bit count output from bit counter 460, memory length switchtiming information, and a weight pattern conforming to parity checkmatrix 600 stored in weight control section 710, weight control section710 sends the values of matrix elements h₁ ^((m))(t) and h₂ ^((m))(t) atthat timing to weight multipliers 420-0 through 420-M and 430-0 through430-M.

Here, memory length switch timing information denotes a transmissioninformation sequence index that switches memory length M of parity checkmatrix 600. For example, if three kinds of memory length M are used,memory length switch timing information can have two values. That is tosay, as memory lengths, memory length switch timing information has atiming information index that switches from M=5 to M=4, and a timinginformation index that switches from M=4 to M=3.

FIG. 11 shows a sample configuration of weight control section 710 whenusing three kinds of memory length M: M=5, 4, and 3. Weight controlsection 710 in FIG. 11 comprises selectors 711 and 715, and weightpattern storage sections 712 through 714. Below, an index indicatingtiming for switching from memory length M=5 to M=4 is referred to asmemory length switch timing information 1, and an index indicatingtiming for switching from memory length M=4 to M=3 is referred to asmemory length switch timing information 2.

Selector 711 has a bit count and memory length switch timing information1 and 2 as input, and if bit count≦memory length switch timinginformation 1, sends the bit count to weight pattern storage section712.

On the other hand, if bit count>memory length switch timing information1, and bit count≦memory length switch timing information 2, selector 711sends the bit count to weight pattern storage section 713.

Furthermore, if bit count>memory length switch timing information 2,selector 711 sends the bit count to weight pattern storage section 714.

Weight pattern storage section 712 stores the weight pattern indicatedby weight pattern 716, and outputs h_(a1), h_(a2), h₃, and h_(a4) toselector 715 periodically as the bit count increases. Weight pattern 716comprises matrix elements h₁ ^((m))(t) and h₂ ^((m))(t) (where m=0, . .. , 5) of an LDPC-CC parity check matrix for a case in which memorylength M=5.

Weight pattern storage section 713 stores the weight pattern indicatedby weight pattern 717, and outputs h_(b1), h_(b2), and h_(b3) toselector 715 periodically as the bit count increases. Weight pattern 717comprises matrix elements h₁ ^((m))(t) and h₂ ^((m))(t) (where m=0, . .. , 4) of an LDPC-CC parity check matrix for a case in which memorylength M=4, and h₁ ⁽⁵⁾=0 and h₂ ⁽⁵⁾=0. When memory length M=4, thenumber of h_(b1), h_(b2), h_(b3) weight pattern elements is 10, butLDPC-CC encoder 700 is equipped with 12 weight multipliers 420-0 through420-M and 430-0 through 430-M capable of handling memory length M=5.Consequently, in weight pattern 717, the h₁ ⁽⁵⁾ and h₂ ⁽⁵⁾ weightelements are 0 in any pattern.

Weight pattern storage section 714 stores the weight pattern indicatedby weight pattern 718, and outputs h_(c1), h_(c2), h_(c3), h_(c4),h_(c5), h_(c6), and h_(c7) to selector 715 periodically as the bit countincreases. Weight pattern 718 comprises matrix elements h₁^((m)(t) and h) ₂ ^((m))(t) (where m=0, . . . , 3) of an LDPC-CC paritycheck matrix for a case in which memory length M=3, and h₁ ⁽⁴⁾⁼0, h₂⁽⁴⁾⁼0, h₁ ⁽⁵⁾⁼0, and h₂ ⁽⁵⁾⁼0. In the same way as when memory lengthM=4, in weight pattern 718, the h₁ ⁽⁴⁾, h₂ ⁽⁴⁾, h₁ ⁽⁵⁾, and h₂ ⁽⁵⁾weight elements are 0 in any pattern.

Selector 715 outputs matrix elements h_(a1), h_(a2), h_(a3), and h_(a4)input from weight pattern storage section 712, matrix elements h_(b1),h_(b2), and h_(b3) input from weight pattern storage section 713, ormatrix elements h_(c1), h_(c2), h_(c3), h_(c4), h_(c5), h_(c6), andh_(c7) input from weight pattern storage section 714, to weightmultipliers 420-0 through 420-M and 430-0 through 430-M.

That is to say, if bit count≦memory length switch timing information 1according to the result of a comparison between a bit count and memorylength switch timing information 1 and 2 in conjunction with selector711, selector 715 outputs matrix elements of weight pattern 716conforming to a parity check matrix with memory length M=5 stored inweight pattern storage section 712 to weight multipliers 420-0 through420-M and 430-0 through 430-M.

On the other hand, if bit count>memory length switch timing information1 and bit count≦memory length switch timing information 2, selector 715outputs matrix elements of weight pattern 717 conforming to a paritycheck matrix with memory length M=4 stored in weight pattern storagesection 713 to weight multipliers 420-0 through 420-M and 430-0 through430-M.

Furthermore, if bit count>memory length switch timing information 2,selector 715 outputs matrix elements of weight pattern 718 conforming toa parity check matrix with memory length M=3 stored in weight patternstorage section 714 to weight multipliers 420-0 through 420-M and 430-0through 430-M.

The operation of LDPC-CC encoder 700 configured as described above willnow be explained.

Transmission information sequence u₁ through u_(n) and terminationsequence x_(1,1) through x_(1,L) are input sequentially to shiftregister 410-1, weight multiplier 420-0, and bit counter 460.

Bit counter 460 counts the number of bits of input transmissioninformation sequence u₁ through u_(n) and termination sequence x_(1,1)through x_(1,L), and outputs the obtained bit count to weight controlsection 710.

Weight control section 710 selects weight pattern 716, weight pattern717, or weight pattern 718 according to the result of a comparisonbetween the bit count and memory length switch timing information, andoutputs matrix elements of the selected weight pattern to weightmultipliers 420-0 through 420-M and 430-0 through 430-M.

Specifically, if bit count≦memory length switch timing information 1,matrix elements of weight pattern 716 conforming to a parity checkmatrix with memory length M=5 are output to weight multipliers 420-0through 420-M and 430-0 through 430-M.

If bit count>memory length switch timing information 1 and bitcount≦memory length switch timing information 2, matrix elements ofweight pattern 717 conforming to a parity check matrix with memorylength M=4 are output to weight multipliers 420-0 through 420-M and430-0 through 430-M.

And if bit count>memory length switch timing information 2, matrixelements of weight pattern 718 conforming to a parity check matrix withmemory length M=3 are output to weight multipliers 420-0 through 420-Mand 430-0 through 430-M.

In this way, the number of bits of a past transmission codeword sequencenecessary for generating a transmission codeword sequence can be reducedas a transmission codeword sequence approaches its end.

As described above, according to this embodiment, weight control section710 stores weight patterns 716,717, and 718 conforming to parity checkmatrices with different memory lengths, and when input bits are aninformation sequence, a weight pattern with a shorter memory length isused toward the rear of the information sequence. Since terminationsequence length L can be made shorter as memory length M decreases,using a weight pattern with a shorter memory length toward the rear ofan information sequence enables termination sequence length L to be madeshorter and degradation of transmission efficiency to be suppressed.

In this embodiment, a case has been described by way of example in whichmemory length M is decreased by 1 at a time—from 5 to 4 to 3 —as therear of a transmission information sequence is approached, but this isnot a limitation, and an effect of suppressing transmission efficiencydegradation through a reduction in the termination sequence transmissionamount can still be obtained by the present invention if a parity checkmatrix for which reduction is performed to an arbitrary memory length,or for which a memory length reduction amount is set arbitrarily, isused.

(Embodiment 3)

In this embodiment, descriptions are given of a parity check matrix thatis designed so that the coding rate of LDPC-CC decreases toward the rearof a transmission information sequence in order to reduce transmissionerrors in the rear part of a information sequence by reducing the numberof termination sequences, and a configuration of an LDPC-CC encoder thatis based on that parity check matrix.

FIG. 12 shows an example of a parity check matrix according to thisembodiment. Parity check matrix 800 in FIG. 12 is an example of a casewith memory length M=5 and transmission information sequence length n.Parity check matrix 800 differs from a conventional LDPC-CC parity checkmatrix in that coding rate R decreases from ½ to ⅓ to ¼ successively asthe index of transmission codeword sequence u₁ increases.

That is to say, as shown in FIG. 12, when parity check matrix 800 isused encoding is performed for transmission information sequence u_(i)through u_(i+7) with a coding rate ½, and transmission codewordsequences v_(1,1) through v_(1,i+7) and v_(2,1) through v_(2,i+7) areacquired. For transmission information u_(i+8) through u_(i+11),encoding is performed with a coding rate ⅓, and transmission codewordsequences v_(1,i+8) through v_(1,i+11), v_(2,i+8) through v_(2,i+11),and v_(3,i+8) through v_(3,i+11) are acquired. And for transmissioninformation u_(i+12) through u_(i+15), encoding is performed with acoding rate ¼, and transmission codeword sequences v_(1,i+12) throughv_(1,i+15), v_(2,i+12) through v_(2,i+15), v_(3,i+12) throughv_(3,i+15), and v_(4,i+12) through v_(4,i+15) are acquired.

Thus, by performing LDPC-CC encoding using parity check matrix 800 shownin FIG. 12, an LDPC-CC codeword with a lower coding rate can begenerated toward the rear of a transmission codeword sequence. Sinceerror correction capability is higher the lower the coding rate, thisenables a bit error occurring in the rear part of an informationsequence to be corrected even if an entire termination sequence is nottransmitted.

Next, we describe a configuration of an LDPC-CC encoder that performsLDPC-CC encoding using parity check matrix 800 in FIG. 12 with referenceto the accompanying drawings.

FIG. 13 is a block diagram showing a main configuration of an LDPC-CCencoder according to this embodiment.

LDPC-CC encoder 900 in FIG. 13 comprises shift registers 910-1-1 through910-c-M, weight multipliers 920-1-1-0 through 920-c-c-M, modulo 2 adders930-1 through 930-c-1, bit counter 940, and weight control section 950.

The shift registers, weight multipliers, bit counter, and weight controlsection in LDPC-CC encoder 900 are similar to the shift registers,weight multipliers, bit counter, and weight control section inconventional use and in above Embodiments 1 and 2, and thereforedescriptions thereof are omitted here.

Based on a bit count output from bit counter 940, coding rate switchtiming information, and a weight pattern conforming to a parity checkmatrix stored in weight control section 950, weight control section 950sends the values of parity check matrix elements h_(1,2) ^((m))(t),h_(2,2) ^((m))(t), h_(c,c) ^((m))(t) at that timing to weightmultipliers 920-1-1-0 through 920-c-c-M.

Here, coding rate switch timing information denotes a transmissioninformation sequence index that switches coding rate R of parity checkmatrix 800. For example, if three kinds of coding rate R are used,coding rate switch timing information can have two values. That is tosay, when using coding rate R=½, ⅓, and ¼, coding rate switch timinginformation has a timing information index that switches from R=½ toR=⅓, and a timing information index that switches from R=⅓ to R=¼.

The configuration and weight pattern switching processing of weightcontrol section 950 are similar to those of weight control section 710,and therefore descriptions thereof are omitted here.

As described above, according to this embodiment, weight control section950 stores a plurality of weight patterns conforming to LDPC-CC paritycheck matrices with different coding rates, and when input bits are aninformation sequence, a weight pattern with a lower coding rate is usedtoward the rear of the information sequence. Since error correctioncapability is higher the lower the coding rate, this enables degradationof transmission efficiency to be suppressed while correcting bit errorsoccurring in the rear part of an information sequence, even if atermination sequence is reduced.

(Embodiment 4)

In this embodiment, a transmitting apparatus is described that isequipped with a termination sequence puncturing section that reduces atermination sequence amount by puncturing some bits of a terminationsequence after LDPC-CC encoding in order to reduce the number oftermination sequences in an LDPC-CC.

FIG. 14 is a block diagram showing a main configuration of atransmitting apparatus according to this embodiment. Transmittingapparatus 1000 in FIG. 14 comprises LDPC-CC encoding section 1010,termination sequence puncturing section 1020, interleaving section 1030,modulation section 1040, control information generation section 1050,radio section 1060, and transmitting antenna 1070.

LDPC-CC encoding section 1010 performs LDPC-CC encoding processing on aninput sequence in which a termination sequence has been added to atransmission information sequence, and outputs a encoded transmissioncodeword sequence to termination sequence puncturing section 1020.

Termination sequence puncturing section 1020 performs puncturing on atermination sequence within a transmission codeword sequence, andoutputs a punctured termination sequence to interleaving section 1030.Puncturing processing will be described later herein.

Interleaving section 1030 performs sequence order rearrangementprocessing (interleaving) on a transmission codeword sequence, andoutputs a interleaved transmission codeword sequence to modulationsection 1040.

Modulation section 1040 modulates a interleaved transmission codewordsequence using a modulation method such as PSK (Phase Shift Keying), QAM(Quadrature Amplitude Modulation) and so on, and outputs a transmissionmodulated symbol sequence to radio section 1060.

Control information generation section 1050 generates controlinformation necessary for transmitting and receiving signals between thetransceiver and the receiver, and sends this control information tomodulation section 1040. Control information includes the modulationmethod and transmission information sequence length, a preamble signalfor time/frequency synchronization, and so forth.

Radio section 1060 performs radio modulation processing such as D/A(Digital to Analog) conversion, frequency conversion, and RF (RadioFrequency) filtering processing on a transmission modulated symbolsequence, generates a transmission RF signal, and transmits this signalvia transmitting antenna 1070.

The operation of transmitting apparatus 1000 configured as describedabove will now be explained, focusing mainly on puncturing processing bytermination sequence puncturing section 1020. In the followingdescription, it is assumed that LDPC-CC coding rate is R=b/c in LDPC-CCencoding section 1010.

In LDPC-CC encoding section 1010, LDPC-CC encoding processing isexecuted on an input sequence in which a termination sequence has beenadded to transmission information sequence u_(i) (where i=1, n), andtransmission codeword sequence [v_(k,i) x_(k,j)] is acquired. Here, k=1,. . . , c and j=1, . . . , L, where L denotes the sequence length of atermination sequence. The LDPC-CC encoding method is described inNon-Patent Document 1 and Non-Patent Document 2, and therefore adescription thereof is omitted here.

in termination sequence puncturing section 1020, puncturing processingis executed on x_(k,j) corresponding to a termination sequence withintransmission codeword sequence [v_(k,i) x_(k,j)] output from LDPC-CCencoding section 1010.

FIG. 15 shows an example of puncturing executed by termination sequencepuncturing section 1020. FIG. 15 shows an example of a case in whichcoding rate R=½ (b=1, c=2), in which the upper part indicates x_(1,1)through x_(1,L), and the lower part indicates x_(2,1) through x_(2,L),and each sequence is input to termination sequence puncturing section1020 in left-to-right order. In FIG. 15, diagonally hatched x_(k,j) bitsrepresent bits punctured by termination sequence puncturing section1020. As shown in FIG. 15, in this embodiment termination sequencepuncturing section 1020 uses a lower puncturing frequency for bits inthe front part of a termination sequence, and uses a higher puncturingfrequency for bits in the rear part of a termination sequence.

In LDPC-CC encoding, the more to the front a part of a terminationsequence is, the nearer it is to a transmission information sequence,and therefore the rear part of a termination sequence has less effect ontransmission codeword sequence v_(k,i) than the front part. Therefore,by having termination sequence puncturing section 1020 increase theproportion of punctured bits toward the rear of a termination sequence,the termination sequence transmission amount can be reduced whilesuppressing degradation of the error rate of an information sequence dueto puncturing.

A punctured transmission codeword sequence is interleaved byinterleaving section 1030, and modulation is executed on the interleavedtransmission codeword sequence and control information by modulationsection 1040. A modulated symbol sequence has radio modulationprocessing executed on it by radio section 1060, and a transmission RFsignal is transmitted via transmitting antenna 1070.

As described above, in this embodiment transmitting apparatus 1000 isequipped with termination sequence puncturing section 1020 thatpunctures a termination sequence included in a sequence after LDPC-CCencoding, and termination sequence puncturing section 1020 increases theproportion of punctured bits toward the rear of a termination sequence.

By using a puncture pattern having a low puncturing frequency for bitsin the front part of a termination sequence, and using a puncturepattern having a high puncturing frequency for bits in the rear part ofa termination sequence, bits having relatively little effect ontransmission codeword sequence v_(k,i) during encoding—that is, bits inthe rear part of a termination sequence—are punctured preferentially,enabling the termination sequence transmission amount to be reducedwhile suppressing degradation of the error rate of an informationsequence due to puncturing.

Puncture patterns in termination sequence puncturing section 1020 arenot limited to the puncture patterns shown in FIG. 15, and the effect ofthe present invention can also be achieved by using another puncturepattern with a higher puncturing frequency for rearward bits of atermination sequence than for forward bits.

(Embodiment 5)

In this embodiment, a transmitting apparatus and receiving apparatus aredescribed that are equipped with a function that compensates fortransmission errors that occur due to a reduction in the number oftransmitted termination sequences by retransmitting part or all of atermination sequence.

FIG. 16 is a block diagram showing a main configuration of atransmitting apparatus according to this embodiment. In the descriptionof this embodiment, configuration parts identical to those in FIG. 14are assigned the same reference numbers as in FIG. 14, and descriptionsthereof are omitted. As compared with transmitting apparatus 1000 inFIG. 14, transmitting apparatus 1100 in FIG. 16 employs a configurationthat additionally includes buffers 1110 and 1120, receiving antenna1130, response signal detection section 1140, retransmission controlsection 1150, and transmission sequence selection section 1160.

Buffer 1110 stores a punctured transmission codeword sequence that hasbeen punctured by termination sequence puncturing section 1020, andbuffer 1120 stores a puncture bit sequence that has been punctured bytermination sequence puncturing section 1020.

Response signal detection section 1140 detects a response signal sentfrom receiving apparatus 1200 described later herein from a receivedsignal received via receiving antenna 1130, and sends the detectedresponse signal to retransmission control section 1150.

Based on the response signal, retransmission control section 1150creates retransmission control information. Specifically, retransmissioncontrol section 1150 creates the following four categories ofretransmission control information based on the response signal.

(0) Retransmission control information “0”: No retransmission

(1) Retransmission control information “1”: Retransmission of entiretransmission codeword sequence

(2) Retransmission control information “2”: Retransmission oftransmission codeword sequence after puncturing

(3) Retransmission control information “3”: Retransmission of puncturebit sequence

The correspondence between a response signal and retransmission controlinformation will be described later herein. Retransmission controlsection 1150 outputs retransmission control information to transmissionsequence selection section 1160 and control information generationsection 1050.

Transmission sequence selection section 1160 selects a transmissioncodeword sequence to be output to interleaving section 1030 according tothe retransmission control information output from retransmissioncontrol section 1150. Specifically, in the case of retransmissioncontrol information “0”, transmission sequence selection section 1160sends a new transmission codeword sequence output from terminationsequence puncturing section 1020 to interleaving section 1030.

In the case of retransmission control information “1”, transmissionsequence selection section 1160 regenerates a transmission codewordsequence prior to being punctured by termination sequence puncturingsection 1020 from sequences stored in buffer 1110 and buffer 1120, andsends the regenerated transmission codeword sequence to interleavingsection 1030.

In the case of retransmission control information “2”, transmissionsequence selection section 1160 sends a punctured transmission codewordsequence stored in buffer 1110 to interleaving section 1030.

And in the case of retransmission control information “3”, transmissionsequence selection section 1160 sends a puncture bit sequence stored inbuffer 1120 to interleaving section 1030 as a transmission codewordsequence.

FIG. 17 is a block diagram showing a main configuration of a receivingapparatus according to this embodiment. Receiving apparatus 1200 in FIG.17 comprises receiving antenna 1201, radio section 1202, quadraturedemodulation section 1203, channel fluctuation estimation section 1204,control information detection section 1205, logarithmic likelihoodcomputation section 1206, deinterleaving section 1207, terminationsequence depuncturing section 1208, sum-product decoding section 1209,buffer 1210, error detection section 1211, response signal generationsection 1212, and transmitting antenna 1213.

Receiving antenna 1201 receives a transmission RF signal transmittedfrom transmitting apparatus 1100, and sends this signal to radio section1202.

Radio section 1202 performs radio demodulation processing such as REfiltering processing, frequency conversion, and A/D (Analog to Digital)conversion, and sends a radio-demodulated baseband signal to quadraturedemodulation section 1203.

Quadrature demodulation section 1203 detects I-channel and Q-channelbaseband signals, and sends these to channel fluctuation estimationsection 1204, control information detection section 1205, andlogarithmic likelihood computation section 1206.

Using a known signal included in the baseband signals, channelfluctuation estimation section 1204 estimates channel fluctuation in aradio channel between transmitting apparatus 1100 and receivingapparatus 1200.

Control information detection section 1205 detects control informationincluded in a baseband signal, and sends the detected controlinformation to logarithmic likelihood computation section 1206. Controlinformation detection section 1205 also detects retransmission controlinformation included in the control information, and sends the detectedretransmission control information to termination sequence depuncturingsection 1208 and buffer 1210.

Using a baseband signal, logarithmic likelihood computation section 1206finds a logarithmic likelihood ratio of each codeword bit, and sends theobtained logarithmic likelihood ratio to deinterleaving section 1207.

Using processing that is the reverse of the rearrangement processingperformed by interleaving section 1030 of transmitting apparatus 1000,deinterleaving section 1207 rearranges a logarithmic likelihood ratiosequence into its original order, and sends a deinterleaved logarithmiclikelihood ratio to termination sequence depuncturing section 1208.

Termination sequence depuncturing section 1208 performs depuncturing ona logarithmic likelihood ratio output from deinterleaving section 1207according to retransmission control information output from controlinformation detection section 1205. Depuncturing processing will bedescribed later herein.

Sum-product decoding section 1209 performs sum-product decoding using alogarithmic likelihood ratio sequence output from termination sequencedepuncturing section 1208, and sends a logarithmic likelihood ratiosequence at the end of sum-product decoding to buffer 1210. Sum-productdecoding section 1209 also acquires a received codeword sequence bymeans of a hard decision using a logarithmic likelihood ratio sequenceat the end of sum-product decoding, and sends the obtained receivedcodeword sequence to error detection section 1211.

Error detection section 1211 performs a parity check using a paritycheck matrix on a received codeword sequence output from sum-productdecoding section 1209, and detects an error. Error detection section1211 performs error detection on individual groups obtained by dividingtransmission information sequence length n at memory length M intervals.Per-group error detection processing will be described later herein.

If an error is not detected as a result of error detection, errordetection section 1211 outputs only a received information sequencewithin a received codeword sequence as a received sequence.

Response signal generation section 1212 generates a response signalaccording to error detection information output from error detectionsection 1211. For example, if error detection information indicates “noerror”, response signal generation section 1212 generates an ACK signalto inform transmitting apparatus 1100 that reception has been achievedcorrectly.

On the other hand, if error detection information indicates “errorpresent”, response signal generation section 1212 generates a NACKsignal to inform transmitting apparatus 1100 that reception has not beenperformed correctly.

If, based on the results of per-group error detection, errors haveoccurred across an entire received codeword sequence, or an error hasoccurred only in a group near the front or middle of a received codewordsequence, response signal generation section 1212 generates NACK:type-Irequesting retransmission of an entire transmission codeword sequence,or NACK:type-II requesting retransmission of a transmission codewordsequence after termination sequence puncturing. Also, if an error hasoccurred only in a group at the rear of a received codeword sequence,response signal generation section 1212 generates NACK:type-IIIrequesting retransmission of only a bit sequence punctured bytermination sequence puncturing section 1020.

Transmitting antenna 1213 transmits an ACK or NACK signal output fromresponse signal generation section 1212 to transmitting apparatus 1100.

The operation of transmitting apparatus 1100 and receiving apparatus1200 configured as described above will now be explained, focusingmainly on retransmission and decoding processing.

A transmission RF signal transmitted from transmitting apparatus 1100 isreceived via receiving antenna 1201 of receiving apparatus 1200, and hasradio demodulation processing executed on it by radio section 1202. Aradio-demodulated signal is demodulated to a baseband signal byquadrature demodulation section 1203.

Control information included in a baseband signal is detected by controlinformation detection section 1205. Also, retransmission controlinformation included in the control information is detected by controlinformation detection section 1205.

In logarithmic likelihood computation section 1206, a logarithmiclikelihood ratio of each transmitted codeword bit is found from abaseband signal, and in deinterleaving section 1207 the order of alogarithmic likelihood ratio sequence is rearranged using processingthat is the reverse of rearrangement processing performed byinterleaving section 1030 in transmitting apparatus 1100.

In termination sequence depuncturing section 1208, a logarithmiclikelihood ratio is depunctured according to the type of retransmissioncontrol information output from control information detection section1205.

In the Case of (0) Retransmission Control Information “0”

Termination sequence depuncturing section 1208 inserts LLR=0 at aposition corresponding to a position of a bit punctured by terminationsequence puncturing section 1020 and generates (depunctures) alogarithmic likelihood ratio sequence. Termination sequence depuncturingsection 1208 sends a depunctured logarithmic likelihood ratio sequenceto sum-product decoding section 1209. In the case of retransmissioncontrol information “0”, unlike the cases of retransmission controlinformation “1” through “3” described later herein, termination sequencedepuncturing section 1208 performs logarithmic likelihood ratio sequencedepuncturing without using a logarithmic likelihood ratio sequencestored in buffer 1210.

In the Case of (1) Retransmission Control Information “1”

Buffer 1210 sends a stored past logarithmic likelihood ratio sequence totermination sequence depuncturing section 1208. Termination sequencedepuncturing section 1208 combines a logarithmic likelihood ratiosequence output from deinterleaving section 1207 and a logarithmiclikelihood ratio sequence output from buffer 1210, and sends apost-combining logarithmic likelihood ratio sequence to sum-productdecoding section 1209.

In the Case of (2) Retransmission Control Information “2”

Buffer 1210 sends a stored past logarithmic likelihood ratio sequence totermination sequence depuncturing section 1208. Termination sequencedepuncturing section 1208 depunctures a logarithmic likelihood ratiosequence output from deinterleaving section 1207 in the same way as inthe case of retransmission control information “0”, combines adepunctured logarithmic likelihood ratio sequence and a logarithmiclikelihood ratio sequence output from buffer 1210, and sends apost-combining logarithmic likelihood ratio sequence to sum-productdecoding section 1209.

In the Case of (3) Retransmission Control Information “3”

Buffer 1210 sends a stored past logarithmic likelihood ratio sequence totermination sequence depuncturing section 1208. Termination sequencedepuncturing section 1208 inserts an LLR of a position corresponding toa bit position punctured by termination sequence puncturing section 1020within a logarithmic likelihood ratio sequence output from buffer 1210in a logarithmic likelihood ratio sequence output from deinterleavingsection 1207, and generates (depunctures) a logarithmic likelihood ratiosequence. Termination sequence depuncturing section 1208 sends adepunctured logarithmic likelihood ratio sequence to sum-productdecoding section 1209.

Sum-product decoding section 1209 performs sum-product decoding using alogarithmic likelihood ratio sequence output from termination sequencedepuncturing section 1208. Sum-product decoding section 1209 sends alogarithmic likelihood ratio sequence at the end of sum-product decodingto buffer 1210. Sum-product decoding section 1209 also sends a receivedcodeword sequence obtained by means of a hard decision on a logarithmiclikelihood ratio sequence at the end of sum-product decoding to errordetection section 1211.

Error detection section 1211 performs a parity check using a paritycheck matrix on a received codeword sequence output from sum-productdecoding section 1209, and detects an error. A parity check is performedbased on whether or not a received codeword sequence satisfies Equation(6).

[6]v _(t) H ₀ ^(T)(t)+v _(t−1) H ₁ ^(T)(t)+ . . . +v _(t−m) _(s) H _(m)_(s) ^(T)(t)=0 . . .   (Equation 6)

By performing a parity check using Equation (6), error detection section1211 can detect an error in individual groups obtained by dividingtransmission information sequence length n at memory length M intervals.Therefore, by comparing per-group error detection results, it ispossible to detect where there are many errors within a receivedcodeword sequence.

Thus, with a parity check, a position at which an error has beendetected is known, and it is therefore possible to identify from aposition at which an error has been detected whether or not that erroris due to termination sequence puncturing. Therefore, if an error is dueto termination sequence puncturing, a decrease in transmissionefficiency due to retransmission can be suppressed by having responsesignal generation section 1212 described later herein generate aresponse signal (NACK:type-III) indicating a retransmission request foronly a punctured bit.

Error detection section 1211 outputs per-group parity check results toresponse signal generation section 1212 as error detection information.As an example of error detection information, vector E=[e₁, e₂, e_(J−1),e_(J)] may be used. Here, J is a number of groups on which errordetection is performed, and e_(i)=0 is set if an error is not detectedin a parity check of an i'th group (where i=1, . . . , J), wherease_(J)=1 is set if an error is detected.

Response signal generation section 1212 generates a response signalaccording to error detection information output from error detectionsection 1211. Specifically, if vector E is an all-zero vector, it isdetermined that an error has not been detected, and response signalgeneration section 1212 generates an ACK signal. On the other hand, ifone or more elements having a value of 1 are included in vector E, it isdetermined that an error has been detected, and response signalgeneration section 1212 generates a NACK signal.

From a position at which a vector E element is 1, response signalgeneration section 1212 can estimate in group units whereabouts in areceived codeword sequence an error occurred. If errors have occurredacross an entire received codeword sequence, or an error has occurredonly in a group near the front or middle of a received codewordsequence, response signal generation section 1212 generates NACK:type-Irequesting retransmission of an entire transmission codeword sequence,or NACK:type-II requesting retransmission of a transmission codewordsequence after termination sequence puncturing. If an error has occurredonly in a group at the rear of a received codeword sequence, responsesignal generation section 1212 generates NACK:type-III requestingretransmission of only a bit punctured by termination sequencepuncturing section 1020.

An ACK or NACK signal output from response signal generation section1212 is transmitted to transmitting apparatus 1100 via transmittingantenna 1213.

In LDPC-CC encoding section 1010 of transmitting apparatus 1100, LDPC-CCencoding processing including termination is executed on transmissioninformation sequence u_(i) (where i=1, . . . , n), and transmissioncodeword sequence [v_(k,i) x_(k,j)] is acquired. In termination sequencepuncturing section 1020, puncturing processing is executed on x_(k,j)corresponding to a termination sequence within transmission codewordsequence [v_(k,i) x_(k,j)] output from LDPC-CC encoding section 1010.

A punctured transmission codeword sequence is output to buffer 1110 andtransmission sequence selection section 1160, and a punctured puncturebit sequence is output to buffer 1120.

A response signal transmitted from receiving apparatus 1200 is detectedby response signal detection section 1140 from a received signalreceived via receiving antenna 1130, and retransmission controlinformation is generated by retransmission control section 1150according to the response signal as shown below.

-   -   (1) If the response signal is ACK, retransmission control        information “0” is created.    -   (2) If the response signal is NACK:type-I, retransmission        control information “I” is created.    -   (3) If the response signal is NACK:type-II, retransmission        control information “2” is created.    -   (4) If the response signal is NACK:type-III, retransmission        control information “3” is created.

A transmission codeword sequence is selected by transmission sequenceselection section 1160 based on the retransmission control informationoutput from retransmission control section 1150.

Specifically, in the case of retransmission control information “0”, anew transmission codeword sequence output from termination sequencepuncturing section 1020 is selected; in the case of retransmissioncontrol information “1”, a transmission codeword sequence prior totermination sequence puncturing is selected; in the case ofretransmission control information “2”, a punctured transmissioncodeword sequence stored in buffer 1110 is selected; and in the case ofretransmission control information “3”, a puncture bit sequence storedin buffer 1120 is selected as a transmission codeword sequence.

In this way, when an error is detected by error detection section 1211of receiving apparatus 1200, only a sequence affecting the error isretransmitted, enabling a decrease in transmission efficiency due toretransmission to be suppressed.

A selected transmission codeword sequence is interleaved by interleavingsection 1030, and modulation is executed on the interleaved transmissioncodeword sequence and control information by modulation section 1040.Control information includes retransmission control information toenable receiving apparatus 1200 to determine what kind of signal hasbeen transmitted.

As described above, according to this embodiment transmitting apparatus1100 is equipped with buffer 1120 that stores a termination sequencepunctured by termination sequence puncturing section 1020, and transmitsthe termination sequence stored in buffer 1120 when a retransmissionrequest is sent from receiving apparatus 1200. With a parity check, aposition at which an error has been detected is known, and it istherefore possible to identify from a position at which an error hasbeen detected whether or not that error is due to termination sequencepuncturing. Therefore, if an error is due to termination sequencepuncturing, a decrease in transmission efficiency due to retransmissioncan be suppressed by retransmitting only a bit punctured by terminationsequence puncturing section 1020.

In this embodiment, a transmitting apparatus using the puncture patternshown in FIG. 15 has been described as an example, but this is not alimitation, and the effect described in this embodiment can also beobtained when another arbitrary puncture pattern is used.

Also, provision may be made for termination sequence puncturing section1020 to use a puncture pattern whereby an entire termination sequence ispunctured, and for transmitting apparatus 1100 not to transmit anytermination sequence at all at the time of an initial transmission. Thisenables a decrease in transmission efficiency due to terminationsequence transmission to be avoided. In this case, the effect describedin this embodiment can be obtained by transmitting a terminationsequence not transmitted at the time of an initial transmission whenNACK:type-III is transmitted from receiving apparatus 1200.

This embodiment has been described as using retransmission controlinformation “0” through “3”, and using ACK and NACK:type-I throughNACK:type-III as response signals, but this is not a limitation, and theeffect of the present invention can also be obtained by using anothermethod whereby it can be determined whether or not a bit error occurredbecause of termination sequence puncturing, and a response signalcapable of reporting this to transmitting apparatus 1100 is transmitted.

In this embodiment, a case has been described in which transmittingapparatus 1100 retransmits transmission codeword sequences stored instorage section 110 and buffer 1120 in the case of retransmissioncontrol information “1” or “2”, but provision may also be made for aretransmission sequence to be encoded by LDPC-CC encoding section 1010and then transmitted. A configuration diagram of a transmittingapparatus in this case is shown in FIG. 18. In the description of thetransmitting apparatus in FIG. 18, configuration parts identical tothose in FIG. 16 are assigned the same reference numbers as in FIG. 16,and descriptions thereof are omitted.

As compared with transmitting apparatus 1100 in FIG. 16, transmittingapparatus 1300 in FIG. 18 employs a configuration in which buffer 1310and LDPC-CC encoding section 1320 have been added in place of buffer1110 and LDPC-CC encoding section 1010.

Buffer 1310 stores a transmission information sequence. Whenretransmission control information “0” is output from retransmissioncontrol section 1150, buffer 1310 clears the stored transmissioninformation sequence and stores a new transmission information sequence,and also sends the new transmission information sequence to LDPC-CCencoding section 1320. In the case of retransmission control information“1” or “2”, buffer 1310 sends the stored transmission informationsequence to LDPC-CC encoding section 1320. If retransmission controlinformation is “3”, buffer 1310 stores the stored transmissioninformation sequence as it is.

LDPC-CC encoding section 1320 performs LDPC-CC encoding on atransmission information sequence using an arbitrary coding rate. Here,provision may also be made for LDPC-CC encoding section 1320 to performLDPC-CC encoding using different coding rates in an initial transmissionand in a retransmission. By this means, in the event of a retransmissioncontrol information “1” or “2” retransmission request from receivingapparatus 1200, LDPC-CC encoding can be executed using a differentcoding rate with high error correction capability on the sametransmission information sequence when performing a retransmission.

In the case of retransmission control information “0”, provision mayalso be made for buffer 1310 to store a new transmission informationsequence with its order rearranged when updating a stored transmissioninformation sequence to a new transmission information sequence. With anLDPC-CC, errors that occur when a termination sequence is punctured areconcentrated in bits at the rear of a transmission information sequence.Therefore, as a result of buffer 1310 storing a new transmissioninformation sequence with its order rearranged, transmission informationbits located at the rear of a transmission information sequence at thetime of a retransmission are different from those at the time of aninitial transmission, enabling the probability of a bit error occurringin a retransmission to be reduced. An example of a method of rearrangingthe order of a transmission information sequence is to rearrange thesequence in order from the rear, for instance. By so doing, a bitLDPC-CC encoded and transmitted at the rear of a transmissioninformation sequence in an initial transmission becomes a bit LDPC-CCencoded and transmitted at the front in a retransmission, and thereforethe proportion of rearward bits likely to be affected by an error in aninitial transmission that are received correctly is increased.

(Embodiment 6)

In this embodiment, descriptions are given of configurations of atransmitting apparatus and receiving apparatus that are equipped with afunction that reduces bit errors occurring in the rear part of areceived information sequence due to a reduction in the number oftransmitted termination sequences by multistage encoding on bits in therear part of a transmission information sequence beforehand.

FIG. 19 is a block diagram showing a main configuration of atransmitting apparatus according to this embodiment. In the descriptionof this embodiment, configuration parts identical to those in FIG. 14are assigned the same reference numbers as in FIG. 14, and descriptionsthereof are omitted. As compared with transmitting apparatus 1000 inFIG. 14, transmitting apparatus 1400 in FIG. 19 employs a configurationthat additionally includes information sequence division section 1410,outer encoding section 1420, and rearranging section 1430.

Information sequence division section 1410 acquires two sequences bydividing a transmission information sequence into a front part and rearpart. For example, information sequence division section 1410 divides ann-bit transmission information sequence into K bits from the front ofthe transmission information sequence and the remaining n-K bits.Information sequence division section 1410 outputs the divided K-bittransmission information sequence to rearranging section 1430, andoutputs the remaining divided n-K-bit transmission information sequenceto outer encoding section 1420.

Outer encoding section 1420 executes outer encoding on the n-K-bittransmission information sequence resulting from the division byinformation sequence division section 1410. By this means, outerencoding is executed on n-K bits in the rear part of the transmissioninformation sequence, enabling transmission errors occurring in the rearpart of a received information sequence due to a reduction in the numberof transmitted termination sequences to be reduced by encoding gain ofthe outer encoding.

A block code that does not require termination, such as an informationsequence length n-K-bit LDPC-BC, for example, should preferably beapplied as an encoding method for outer encoding. Outer encoding section1420 outputs an outer-encoded transmission information sequence torearranging section 1430.

Rearranging section 1430 has a transmission information sequence frominformation sequence division section 1410 and a transmissioninformation sequence from outer encoding section 1420 as input, andrearranges the order of these transmission information sequences. As therearrangement order, a parity sequence generated by outer encodingsection 1420 is preferentially positioned forward compared with atransmission information sequence input to outer encoding section 1420.

As explained above, with an LDPC-CC, errors that occur when atermination sequence is punctured are concentrated in bits at the rearof a transmission information sequence. Therefore, by having rearrangingsection 1430 preferentially position a parity sequence generated byouter encoding section 1420 forward, the proportion of errors in thatparity sequence is reduced, and outer encoding gain can be improved.

Rearranging section 1430 sends an interleaved transmission informationsequence to LDPC-CC encoding section 1010.

FIG. 20 is a block diagram showing a main configuration of a receivingapparatus according to this embodiment. In the description of thisembodiment, configuration parts identical to those in FIG. 17 areassigned the same reference numbers as in FIG. 17, and descriptionsthereof are omitted. As compared with receiving apparatus 1200 in FIG.17, receiving apparatus 1500 in FIG. 20 employs a configuration in whichresponse signal generation section 1212 and transmitting antenna 1213have been eliminated, and rearranging section 1501, received informationsequence division section 1502, and outer code decoding section 1503have been added.

Rearranging section 1501 rearranges a received information sequencedecoded by sum-product decoding section 1209 according to a rule that isthe reverse of that of rearranging section 1430 in transmittingapparatus 1400, and sends a deinterleaved received information sequenceto received information sequence division section 1502.

Received information sequence division section 1502 divides a receivedinformation sequence output from rearranging section 1501 into tworeceived information sequences using the same rule as informationsequence division section 1410 in transmitting apparatus 1400. Receivedinformation sequence division section 1502 sends a divided K-bitinformation sequence to error detection section 1211, and sends theremaining divided received information sequence to outer code decodingsection 1503.

Outer code decoding section 1503 performs outer code decoding processingon the post-division received information sequence. For example, if aninformation sequence length n-K-bit LDPC-BC has been applied as an outercode in outer encoding section 1420, outer code decoding section 1503performs LDPC-BC decoding using sum-product decoding or BeliefPropagation (BP) decoding. Outer code decoding section 1503 sends adecoded received information sequence to error detection section 1211.

As described above, in this embodiment information sequence divisionsection 1410 acquires two sequences by dividing a transmissioninformation sequence into a front part and rear part, and outer encodingsection 1420 executes outer encoding on bits in the rear part of thetransmission information sequence. By this means, if an error occurs inthe rear part of a received information sequence due to a terminationsequence reduction by LDPC-CC encoding section 1010, that error can becorrected by outer encoding, enabling degradation of reception qualityto be suppressed. Moreover, since outer encoding is not performed on anentire transmission information sequence, but is executed only on therear part of a transmission information sequence that is prone to errorsdue to a termination sequence reduction, a decrease in the coding ratedue to concatenated encoding can be suppressed. Furthermore, byproviding rearranging section 1430, and preferentially positioning partof an outer codeword sequence obtained by outer encoding toward thefront of the transmission information sequence after outer encoding hasbeen executed, the encoding gain of outer encoding can be improved.

In the above description, a case has been described in which informationsequence division section 1410 extracts K transmission informationsequence bits consecutively from the front of a transmission informationsequence, but provision may also be made for information sequencedivision section 1410 to extract K bits consecutively from an arbitraryposition in a transmission information sequence, or to extract K bitsrandomly, and to output the remaining n-K bits to outer encoding section1420. In this way, outer encoding is executed on n-K consecutive bits orn-K random bits of a transmission information sequence, enabling errorsthat occur in a burst to be corrected.

Also, in the above description, a case has been described in whichrearranging section 1430 positions a parity sequence generated by outerencoding section 1420 more forward than a transmission informationsequence input to outer encoding section 1420, but this is not alimitation. For example, provision may also be made for rearrangingsection 1430 to perform rearrangement so that a transmission informationsequence that has not undergone outer encoding, output from informationsequence division section 1410, and a transmission information sequencethat has undergone outer encoding by outer encoding section 1420, aremixed. In this way, bits on which outer encoding has been executed arealso positioned in other than the rear part of a transmission codewordsequence, enabling outer encoding gain to be further improved.

A block diagram showing another main configuration of a receivingapparatus according to this embodiment is shown in FIG. 21. As comparedwith receiving apparatus 1500 in FIG. 20, receiving apparatus 1600 inFIG. 21 employs a configuration that additionally includes receivedinformation sequence combining section 1601.

Received information sequence combining section 1601 acquires a receivedinformation sequence by combining a received information sequence outputfrom received information sequence division section 1502 and a receivedinformation sequence after outer-encoded decoding output from outer codedecoding section 1503, and outputs the acquired received informationsequence to error detection section 1211 and sum-product decodingsection 1209.

In this way, sum-product decoding section 1209 can perform decoding ofan LDPC-CC that is an inner code again while using a receivedinformation sequence that reflects an outer code decoding result, andthrough execution that reflects inner code decoding and outer codedecoding in this way, decoding gain is improved and the number of errorsincluded in a received information sequence can be reduced.

Furthermore, if error correction decoding is performed only on a part inwhich an error has been detected within a received information sequence,using error detection section 1211 error detection results, the numberof computations due to iterative decoding can be reduced. In addition,since an information sequence that has been received without error isconfirmed from error detection section 1211 error detection results,inner code and outer code decoding gain can be improved by making thereception likelihood of those bits +∞ or −∞.

(Embodiment 7)

In Embodiments 4 through 6, cases have been described in whichpuncturing is executed on a termination sequence. In this embodiment, adescription is given of a transmitting apparatus that executespuncturing suitable for a transmission codeword sequence obtained byLDPC-CC encoding, and such a puncturing method.

FIG. 22 is a drawing showing a configuration of a parity check matrixused in this embodiment. Unlike FIG. 1, FIG. 22 shows the configurationof parity check matrix H, not parity check matrix H^(T). If atransmission codeword vector is denoted by v, the relational expressionHv=0 holds true.

In the description of a puncturing method according to this embodiment,a problem when a general puncturing method is applied to abovetransmission codeword sequence v will first be explained. A generalpuncturing method is described in Non-Patent Document 4, for example.Below, a case in which an LDPC-CC is configured using a convolutionalcode with coding rate R=½, (177, 131) is described as an example.

FIG. 23 is a drawing for explaining a general puncturing method. In FIG.23, v_(1,t) and v_(2,t) (where t=1, 2, . . . ) indicate transmissioncodeword sequence v. With a general puncturing method, transmissioncodeword sequence v is divided into a plurality of blocks, andtransmission codeword bits are punctured by using the same puncturing oneach block.

FIG. 23 shows how transmission codeword sequence v is divided intoblocks at 6-bit intervals, and transmission codeword bits are puncturedin a fixed proportion using the same puncture pattern on all blocks. InFIG. 23, circled bits indicate bits that are punctured (bits that arenot transmitted), and v_(2,1), v_(2,3), v_(2,4), v_(2,6), v_(2,7),v_(2,9), v_(2,10), v_(2,12), v_(2,13), and v_(2,15) are selected andpunctured (made non-transmitted bits) so that the coding rate becomes ¾after the puncturing.

Next, the effect on the receiver side (decoding side) will be consideredwhen the kind of general puncturing shown in FIG. 23 is executed on atransmission codeword sequence obtained by encoding using an LDPC-CC.Below, a case in which BP decoding is used on the receiver side(decoding side) will be considered. In BP decoding, decoding processingis performed based on a parity check matrix. FIG. 24 shows thecorrespondence between transmission codeword sequence v and parity checkmatrix H. In FIG. 24, circled bits are transmission codeword bits thatare punctured by puncturing. As a result, bits corresponding to a 1inside a square in parity check matrix H cease to be included in atransmission codeword sequence. As a result, when BP decoding isperformed there is no initial logarithmic likelihood ratio for a bitcorresponding to a 1 inside a square, and therefore the logarithmiclikelihood ratio is set to 0.

In BP decoding, row computation and column computation are performediteratively. Therefore, if two or more bits for which there is noinitial logarithmic likelihood ratio (bits with a 0 logarithmiclikelihood ratio) (that is, bits corresponding to a 1 inside a square inFIG. 24) are included in the same row, logarithmic likelihood ratioupdating is not performed by only row computation for that row until thelogarithmic likelihood ratio of a bit for which there is no initiallogarithmic likelihood ratio (a bit with a 0 logarithmic likelihoodratio) is updated by column computation. That is to say, reliability isnot propagated by only row computation, and iteration of row computationand column computation is necessary in order to propagate reliability.Therefore, if there are many such rows, reliability is not propagated ina case such as when there is a limit on the number of iterationprocesses in BP decoding, causing degradation of reception quality. Inthe example shown in FIG. 24, rows 1710 are rows for which reliabilityis not propagated by only row computation—that is, rows that causedegradation of reception quality.

On the other hand, when a puncturing method according to this embodimentis used, the number of rows for which reliability is not propagated byonly row computation can be reduced. In this embodiment, transmissioncodeword bit puncturing is performed, using a first puncture pattern anda second puncture pattern whereby more bits are punctured than with thefirst puncture pattern, for each transmission codeword bit processingunit. This will now be explained using FIG. 25 and FIG. 26.

FIG. 25 is a drawing for explaining a puncturing method according tothis embodiment. As in FIG. 23, v_(1,t) and v_(2,t) (where t=1, 2, . . .) indicate transmission codeword sequence v, and a case is describedbelow in which one block is composed of 6 bits in the same way as inFIG. 23. Also, it is assumed that a transmission codeword bit processingunit on the receiver side (decoding side) comprises block 1 throughblock 5. The example shown in FIG. 25 shows the way in which v_(2,1),v_(2,3), v_(2,4), v_(2,6), v_(2,7), v_(2,9), v_(2,10), v_(2,12),v_(2,13), and v_(2,15) are punctured as a result of using a firstpuncture pattern that does not perform puncturing for the first block,block 1, and using a second puncture pattern that performs puncturingfor block 2 through block 5. Thus, in this embodiment, puncture patternshaving different coding rates are used, and a range in which few hitsare punctured is provided within a transmission codeword bit processingunit.

FIG. 26 shows the correspondence between transmission codeword sequencev and parity check matrix H in this case. In FIG. 26, although threerows occur that include two or more 1s inside a square in the same row,the number of such rows has been reduced compared with the case shown inFIG. 24. This is due to the fact that puncturing is not executed onblock 1.

Thus, by providing a block on which puncturing is not performed, thenumber of rows causing degradation of reception quality when BP decodingis performed can be reduced. As a result, in lines up to rows 1720 thereis a logarithmic likelihood initially, reliability is dependablypropagated in BP decoding, and post-updating reliability is propagatedto rows 1720, enabling degradation of reception quality to besuppressed. Thus, due to the characteristics of the structure of aconvolutional code based parity check matrix, row reliabilities obtainedby only row computations are propagated sequentially by performingiterative decoding a plurality of times, enabling degradation ofreception quality due to puncturing to be suppressed. Also, since thenumber of rows for which reliability is not propagated by only rowcomputation is reduced, the number of iterations necessary forreliability propagation can be reduced.

In the example shown in FIG. 25, transmitted transmission codeword bitsincrease and transmission speed decreases due to the provision of ablock that is not punctured. However, as long as provision is made forthe relationship N<<M to hold true between number of bits N for whichthe first puncture pattern is used and number of bits M for which thesecond puncture pattern is used, reception quality can be improved whilesuppressing a decrease in transmission speed. In the example shown inFIG. 25, N=6 and M=24, and although the number of additionaltransmission codeword bits is only two, the number of rows for whichlogarithmic likelihood propagation is not performed by only rowcomputation can be reduced from six to three.

A configuration of a transmitting apparatus according to this embodimentwill now be described. FIG. 27 is a block diagram showing a mainconfiguration of a transmitting apparatus according to this embodiment.In the description of this embodiment, configuration parts identical tothose in FIG. 14 are assigned the same reference numbers as in FIG. 14,and descriptions thereof are omitted. As compared with transmittingapparatus 1000 in FIG. 14, transmitting apparatus 1800 in FIG. 27 isequipped with puncturing section 1810 instead of termination sequencepuncturing section 1020. Puncturing section 1810 is equipped with firstpuncturing section 1811, second puncturing section 1812, and switchingsection 1813.

Puncturing section 1810 performs puncturing on a transmission codewordsequence comprising a transmission information sequence and atermination sequence, and outputs a punctured transmission codewordsequence to interleaving section 1030.

Specifically, puncturing section 1810 punctures a transmission codewordsequence using a first puncture pattern and a second puncture patternwhereby more bits are punctured than with the first puncture pattern.The first puncture pattern and second puncture pattern have differentproportions of bits that are punctured. Puncturing section 1810punctures a transmission codeword sequence using a puncture pattern suchas shown in FIG. 28, for example. In FIG. 28, (N+M) bits comprise areceiver side (decoding-side) processing unit.

First puncturing section 1811 performs puncturing on a transmissioncodeword sequence using a first puncture pattern. Second puncturingsection 1812 performs puncturing on a transmission codeword sequenceusing a second puncture pattern.

When the puncture pattern shown in FIG. 28 is used, first puncturingsection 1811 does not perform puncturing on an N-bit transmissioncodeword sequence from the start of a receiver side (decoding-side)processing unit, and outputs a transmission codeword sequence input tofirst puncturing section 1811 to switching section 1813. Secondpuncturing section 1812 performs puncturing on a bit (N+1) through (N+M)transmission codeword sequence, and outputs a punctured transmissioncodeword sequence to switching section 1813.

Provision may also be made for first puncturing section 1811 and secondpuncturing section 1812 to determine whether or not to executepuncturing on a transmission codeword sequence based on a control signalfrom control information generation section 1050. According to a controlsignal from control information generation section 1050, switchingsection 1813 outputs either a transmission codeword sequence output fromfirst puncturing section 1811, or a transmission codeword sequenceoutput from second puncturing section 1812, to interleaving section1030.

The operation of transmitting apparatus 1800 configured as describedabove will now be explained, focusing mainly on puncturing processing bypuncturing section 1810. Below, a case in which LDPC-CC encoding section1010 executes LDPC-CC encoding using a convolutional code with codingrate R=½, (177, 131) is described as an example.

In LDPC-CC encoding section 1010, LDPC-CC encoding processing isexecuted on transmission information sequence u_(t) (where t=1, n), andv=(v_(1,t), v_(2,t)) is obtained. In the case of a systematic code,v_(1,t) is transmission information sequence u_(t) and v_(2,t) isparity. Parity v_(2,t) is found based on transmission informationsequence v_(1,t) and a check equation of each row in FIG. 26.

Puncturing processing is executed on coding rate R=½ transmissioncodeword sequence v by puncturing section 1810. For example, when thepuncturing shown in FIG. 25 is used, puncturing is not performed onblock 1 by puncturing section 1810, but bits are punctured in a regularmanner at predetermined intervals on block 2 through block 5. That is tosay, bits v_(2,4) and v_(2,6) are punctured in block 2, bits v_(2,7) andv_(2,9) are punctured in block 3, bits v_(2,10) and v_(2,12) arepunctured in block 4, and bits v_(2,13) and v_(2,15) are punctured inblock 5. In this way, a transmission codeword sequence with coding rateR=¾ is obtained for block 2 through block 5.

A punctured transmission codeword sequence is transmitted to thereceiver side (decoding side) via interleaving section 1030, modulationsection 1040, radio section 1060, and transmitting antenna 1070. At thistime, when the puncture pattern shown in FIG. 25 is used, v_(2,4),v_(2,6), v_(2,7), v_(2,9), v_(2,10), v_(2,12), v_(2,13), and v_(2,15)are not transmitted.

Thus, when the puncture pattern shown in FIG. 25 is used, blocks forwhich puncturing is not performed occur at predetermined intervals. Asshown in FIG. 25, as a result of puncturing not being performed on block1, v_(2,1) and v_(2,3), which were not transmitted when the generalpuncturing method in FIG. 23 was used, are transmitted. Consequently,rows for which reliability is not propagated by only row computationwhen using BP decoding are the three rows shown as rows 1720 in FIG. 26.As can be seen by comparing FIG. 23 and FIG. 25, adding two transmissionbits decreases the number of rows for which reliability is notpropagated by only row computation from six to three. As a result, thenumber of rows for which there is a logarithmic likelihood initiallyincreases, and initial reliability is updated dependably by BP decoding,and furthermore that reliability is propagated to rows 1720 in FIG. 26.

Subsequently, due to the characteristics of the structure of aconvolutional code based parity check matrix, reliabilities present inlarge numbers at the start of the parity check matrix are propagatedsequentially by performing iterative decoding a plurality of times,enabling degradation of reception quality due to puncturing to besuppressed.

In the example shown in FIG. 25, the additional number of bits that cometo be transmitted is only two, and therefore a decrease in transmissionspeed is small and degradation of reception quality can be suppressed.The achievement of this effect is due to the characteristic of anLDPC-CC adopting a form in which places where a 1 is present areconcentrated in a parallelogram-shaped range in a parity check matrix,as shown in FIG. 34. Therefore, there is little possibility of beingable to obtain the same kind of effect by application to the case of anLDPC-BC.

Thus, by providing a block that is not punctured, the number of rowsthat exert an adverse effect when BP decoding is performed can bereduced. To consider transmission efficiency in this case, it isimportant that the relationship N<<M should hold true between bits Nforming a block that is not punctured and bits M forming a block subjectto puncturing. By making N<<M, degradation of reception quality can besuppressed while suppressing degradation of transmission efficiency.

Provision may also be made for puncturing section 1810 to puncture block2 through block 5, to which the second puncture pattern is applied, inaccordance with a predetermined rule instead of randomly.

Puncture computation processing is simpler when puncturing is performedin accordance with a predetermined rule than when puncturing isperformed randomly.

(Other Puncture Patterns)

The puncture pattern used by puncturing section 1810 is not limited tothat in FIG. 28. For example, provision may also be made for puncturingsection 1810 to use a puncture pattern with coding rate R1=⅔ as a firstpuncture pattern, and to use a puncture pattern with coding rate R2=⅚ asa second puncture pattern, as shown in FIG. 29.

Furthermore, puncturing may also be executed with n frames as aprocessing unit on the receiver side (decoding side), as shown in FIG.30A and FIG. 30B. As shown in FIG. 30A, provision may be made for afirst puncture pattern whereby puncturing is not performed to be usedfor N bits from the start of n frames (where n is an integer greaterthan or equal to 1), and for a second puncture pattern wherebypuncturing is performed to be used for bits (N+1) through (N+M).

Alternatively, as shown in FIG. 30B, provision may be made for a firstpuncture pattern with coding rate R1=⅔ to be used for N bits from thestart of n frames, and for a second puncture pattern with coding rateR2=⅚ to be used for bits (N+1) through (N+M).

Also, a pattern may be used whereby fewer bits are punctured bypuncturing toward the rear of a processing unit on the receiver side(decoding side), as shown in FIG. 31A and FIG. 31B. Providing for fewerbits to be punctured by puncturing toward the rear of a processing uniton the receiver side (decoding side) improves reception quality in BPdecoding.

As in the case shown in FIG. 28, as long as provision is made for therelationship N<<M to hold true between number of bits N for which thefirst puncture pattern is used and number of bits M for which the secondpuncture pattern is used, reception quality can be improved whilesuppressing a decrease in transmission speed.

Also, as shown in FIG. 32A, provision may be made for a first puncturepattern whereby puncturing is not performed to be used for N1 bits fromthe start of n frames (where n is an integer greater than or equal to 1)comprising a processing unit on the receiver side (decoding side), for asecond puncture pattern whereby puncturing is performed to be used forbits (N1+1) through (N1+M), and for the first puncture pattern wherebypuncturing is not performed to be used for bits (N1+M+1) through(N1+M+N2).

Moreover, as shown in FIG. 32B, provision may be made for a firstpuncture pattern with coding rate R1=⅔ to be used for N1 bits from thestart of n frames (where n is an integer greater than or equal to 1)comprising a processing unit on the receiver side (decoding side), for asecond puncture pattern with coding rate R2=⅚ to be used for bits (N1+1)through (N1+M), and for the first puncture pattern with coding rate R1=⅔to be used for bits (N1+M+1) through (N1+M+N2).

Parity check matrices for which reliability is high increase when afirst puncture pattern whereby few bits are punctured by puncturing isused in two places in a processing unit on the receiver side (decodingside) (see FIG. 32) as compared with a case in which such a firstpuncture pattern is used in one place (see FIG. 30 and FIG. 31), andtherefore the convergence rate is high when BP decoding is performed,and decoded results can be obtained with a small number of iterations.

The number of places at which a first puncture pattern whereby few bitsare punctured by puncturing is used in an above processing unit is notlimited to two, and may be three or more.

When the number of places at which a first puncture pattern whereby fewbits are punctured by puncturing is used in an above processing unit istwo or more, also, as long as provision is made for the relationshipN<<M to hold true between total number of bits N for which the firstpuncture pattern is used and total number of bits M for which the secondpuncture pattern is used, reception quality can be improved whilesuppressing a decrease in transmission speed.

In FIG. 30, FIG. 31, and FIG. 32, cases have been described in which afirst puncture pattern and second puncture pattern are used for nframes, but n need only be an integer greater than or equal to 1, andapplication is also possible in the case of one frame.

Below, puncture patterns suitable for a transmission codeword sequenceobtained by LDPC-CC encoding will be considered, taking the relationshipto decoding processing timing into consideration.

FIG. 33 is a drawing for explaining decoding processing timing. In FIG.33, received data sequences are each composed of n frames (for example,n OFDM (Orthogonal Frequency Division Multiplexing) symbols: an OFDMsymbol being a symbol composed of all carriers (32 subcarriers) when anOFDM method comprises 32 subcarriers and composes a modulation signal ona subcarrier-by-subcarrier basis). This received data sequence length isa processing unit on the receiver side (decoding side), and the relevantn frames (or n OFDM symbols) are passed to an upper layer as one entity.Generally, there is a time lag until the upper layer fetches data of thenext frame, and therefore timings t3, t6, and t9 in FIG. 33—that is,timings at which the final part of n frames is received—are actuallytaken to be the ends of periods in which BP decoding is performed.

As an LDPC-CC has properties of a convolutional code, in order for dataestimated by BP decoding from timing t2 to be made valid data (data witha high possibility of being correct), it is necessary for BP decoding tobe started before timing t2. For example, in the example shown in FIG.33, in order for estimated data obtained by BP decoding between t2 andt5 to be made valid data, it is necessary for BP decoding to beperformed between t1 and t6. Similarly, in order for estimated dataobtained by BP decoding between t5 and t8 to be made valid data, it isnecessary for BP decoding to be performed between t4 and t9.

When such decoding processing timing is taken into consideration, ifprovision is made for puncturing such that the number of bits puncturedby puncturing becomes smaller in the rear part of a received datasequence composed of n frames, for example, rows for which reliabilityis propagated are included both forward and rearward in a BP decodingprocessing period, and therefore reliability can be propagatedefficiently.

As described above, according to this embodiment provision is made forpuncturing section 1810 to perform transmission codeword bit puncturingusing a first puncture pattern, and a second puncture pattern wherebymore bits are punctured than with the first puncture pattern, for eachtransmission codeword bit processing unit.

By using first and second puncture patterns with different puncturedcoding rates instead of executing puncturing in a fixed proportion,degradation of decoding characteristics due to BP decoding can besuppressed.

Although rows that cause degradation of reception quality inevitablyoccur when puncturing is performed, a method of suppressing degradationof reception quality while suppressing a decrease in transmission speed,such as a puncturing method according to this embodiment, is extremelyimportant in constructing a system offering good performance.

First and second puncture patterns may each be composed of an identicalplurality of sub-patterns. That is to say, provision may be made foridentical sub-puncture-patterns to be used for each of blocks 2 through5, and for transmission codeword bits to be punctured in a regularmanner, as shown in FIG. 25. This enables puncture computationprocessing to be simplified.

Also, a first puncture pattern with a small coding rate need notnecessarily be positioned at the end of n frames, but, as can be seenfrom FIG. 33, may also be provided between t1 and t3, t4 and t6, and t7and t9. Furthermore, since periods t1 to t3, t4 to t6, and t7 to t9 aredetermined by the relationship between a BP decoding processing periodand a period in which valid data is obtained, a suitable position forplacing a first puncture pattern also varies.

In the above description, a puncturing method for a case in which BPdecoding is performed on a convolutional code has been described as anexample, but this is not a limitation, and a puncturing method of thepresent invention can also be implemented in a similar way in the caseof a time-invariant LDPC-CC or time-varying LDPC-CC such as described inNon-Patent Document 1 and Non-Patent Document 5 through Non-PatentDocument 7.

(Embodiment 8)

In this embodiment, descriptions are given of a parity check matrix thatis designed so that LDPC-CC encoding memory length M decreases towardthe front and toward the rear of a transmission information sequence,and a configuration of an LDPC-CC encoder that is based on that paritycheck matrix. Use of such a configuration enables the number of statesof an encoder at the start and end of encoding to be reduced.Consequently, when termination by means of tail-biting described inNon-Patent Document 8 is used, for example, the number of states thatneed to be considered in encoding and decoding can be reduced, enablingencoder and decoder configurations to be simplified.

FIG. 34 shows an example of a parity check matrix according to thisembodiment. Parity check matrix 1900 in FIG. 34 is an example of a casewith coding rate R=b/c=½ and transmission information sequence length n.Parity check matrix 1900 differs from parity check matrix 100 in FIG. 3in that, in parts in which the index of transmission informationsequence u_(t) approaches 1 and approaches n, encoding memory length M1is smaller than memory length M2 of other parts.

Parity check matrix 1900 is an example in which M1=3 and M2=5, but M1and M2 are not limited to these values, and it is only necessary for therelationship M1<M2 to hold true. More particularly, the relationshipM1<<M2 is advantageous in that the number of tail-biting states can bereduced, and the LDPC-CC constraint length for bits in a part other thana part relating to termination can be lengthened. Also, provision may bemade for the number of memory lengths to be made three or more, and forthe memory length to decrease gradually as the index of transmissioninformation sequence u_(t) approaches 1 and approaches n.

As shown in FIG. 34, when parity check matrix 1900 is used encoding isperformed for transmission information sequence u₁ through u₅ withmemory length M1=3, and transmission codeword sequences v_(1,1) throughv_(1,5) and v_(2,1) through v_(2,5) are acquired. For transmissioninformation sequence u_(n6) through u_(n−5), encoding is performed withmemory length M2=5, and transmission codeword sequences v_(1,6) throughv_(1,n−5) and v_(2,6) through v_(2,n−5) are acquired. And fortransmission information sequence u_(n−4) through u_(n), encoding isperformed with memory length M1=3, and transmission codeword sequencesv_(1,n−4) through v_(1,n) and v_(2,n−4) through v_(2,n) are acquired.

As described in Non-Patent Document 8, the number of encoding initialstates and end states is two to the M-th power, where M is the memorylength of an encoder. Therefore, if memory length M1 of an encoderrelating to initial-state and end-state encoding is made smaller, thenumber of states relating to tail-biting can be reduced.

Thus, by performing LDPC-CC encoding using parity check matrix 1900shown in FIG. 34, the number of initial states and end states of anencoder can be reduced, and as a result, the amount of computation andprocessing delay relating to encoding/decoding can be reduced.

A characteristic of an LDPC-CC is that greater encoding gain and abetter error rate characteristic are obtained the larger the value ofmemory length M. Consequently, with parity check matrix 1900, encodinggain can be obtained by increasing the memory length of a part otherthan a part relating to termination.

Next, a configuration of an LDPC-CC encoder that performs LDPC-CCencoding using parity check matrix 1900 in FIG. 34 will be describedwith reference to the accompanying drawings.

FIG. 35 is a block diagram showing a main configuration of an LDPC-CCencoder according to this embodiment. In the description of thisembodiment, configuration parts identical to those in FIG. 6 areassigned the same reference numbers as in FIG. 6, and descriptionsthereof are omitted. As compared with LDPC-CC encoder 400 in FIG. 6,LDPC-CC encoder 2000 in FIG. 35 does not have puncturing section 480 andis equipped with weight control section 2010 instead of weight controlsection 470.

Based on a bit count output from bit counter 460, memory length switchtiming information, and a weight pattern conforming to parity checkmatrix 1900 stored in weight control section 2010, weight controlsection 2010 sends the values of matrix elements h₁ ^((m))(t) and h₂^((m))(t) at the memory length switching timing to weight multipliers420-0 through 420-M and 430-0 through 430-M. Here, M is greater than M1.

Here, memory length switch timing information denotes a transmissioninformation sequence index that switches memory length M of parity checkmatrix 1900. For example, in the case of parity check matrix 1900 shownin FIG. 34, encoding is performed on the front part and rear part of atransmission information sequence using M1=3, and encoding is performedon other parts using M2=5, and therefore memory length switch timinginformation can have two values. That is to say, memory length switchtiming information has a timing information index that switches fromM1=3 to M2=5, and a timing information index that switches from M2=5 toM1=3.

FIG. 36 shows a sample configuration of weight control section 2010 whenusing two kinds of memory length M: M1=3 and M2=5. Weight controlsection 2010 in FIG. 36 comprises selectors 2011 and 2015, and weightpattern storage sections 2012 and 2013. Below, an index indicatingtiming for switching from memory length M1=3 to M2=5 is referred to asmemory length switch timing information 1, and an index indicatingtiming for switching from memory length M2=5 to M1=3 is referred to asmemory length switch timing information 2.

Selector 2011 has a bit count and memory length switch timinginformation 1 and 2 as input, and if bit count memory length switchtiming information 1, sends the bit count to weight pattern storagesection 2012.

On the other hand, if bit count>memory length switch timing information1, and bit count≦memory length switch timing information 2, selector2011 sends the bit count to weight pattern storage section 2013.

Furthermore, if bit count>memory length switch timing information 2,selector 2011 sends the bit count to weight pattern storage section2012.

Weight pattern storage section 2012 stores the weight pattern indicatedby weight pattern 2016, and outputs h_(al), h_(a2), h_(a3), and h_(a4)to selector 2015 periodically as the bit count increases. Weight pattern2016 comprises matrix elements h₁ ^((m))(t) and h₂ ^((m))(t) (where m=0,. . . , 3) of a parity check matrix for a case in which memory lengthM1=3. When memory length M1=3, the number of h_(b1), h_(b2), h_(b3)weight pattern elements is eight, but LDPC-CC encoder 2000 is equippedwith 12 weight multipliers 420-0 through 420-M (where M=5) and 430-0through 430-M (where M=5) capable of handling memory length M2=5.Consequently, in weight pattern 2016, the h₁ ⁽⁴⁾, h₂ ⁽⁴⁾, h₁ ⁽⁵⁾, and h₂⁽⁵⁾ weight elements are 0 in any pattern.

Weight pattern storage section 2013 stores the weight pattern indicatedby weight pattern 2017, and outputs h_(b1), h_(b2), and h_(b3) toselector 2015 periodically as the bit count increases. Weight pattern2017 comprises matrix elements h₁ ^((m))(t) and h₂ ^((m))(t) (where m=0,. . . , 5) of an LDPC-CC parity check matrix for a case in which memorylength M2=5.

Selector 2015 outputs matrix elements h_(a1), h_(a2), h_(a3), and h_(a4)input from weight pattern storage section 2012, and matrix elementsh_(b1), h_(b2), and h_(b3) input from weight pattern storage section2013, to weight multipliers 420-0 through 420-M and 430-0 through 430-M.

That is to say, if bit count≦memory length switch timing information 1according to the result of a comparison between a bit count and memorylength switch timing information 1 and 2 in conjunction with selector2011, selector 2015 outputs matrix elements of weight pattern 2016conforming to a parity check matrix with memory length M1=3 stored inweight pattern storage section 2012 to weight multipliers 420-0 through420-M and 430-0 through 430-M.

On the other hand, if bit count>memory length switch timing information1 and bit count≦memory length switch timing information 2, selector 2015outputs matrix elements of weight pattern 2017 conforming to a paritycheck matrix with memory length M2=5 stored in weight pattern storagesection 2013 to weight multipliers 420-0 through 420-M and 430-0 through430-M.

Furthermore, if bit count>memory length switch timing information 2,selector 2015 outputs matrix elements of weight pattern 2018 conformingto a parity check matrix with memory length M1=3 stored in weightpattern storage section 2012 to weight multipliers 420-0 through 420-Mand 430-0 through 430-M.

The operation of LDPC-CC encoder 2000 configured as described above willnow be explained.

The state of shift registers 410-1 through 410-M is set to S1, and thestate of shift registers 440-1 through 440-M is set to S2. States S1 andS2 are decide by a transmission sequence. Transmission informationsequence u₁ through u_(n) is output sequentially to shift register410-1, weight multiplier 420-0, and bit counter 460.

Bit counter 460 counts the number of bits of input transmissioninformation sequence u₁ through u_(n) and termination sequence x_(1,1)through x_(1,L), and outputs the obtained bit count to weight controlsection 2010.

Weight control section 2010 selects either weight pattern 2016 or weightpattern 2017 according to the result of a comparison between the bitcount and memory length switch timing information, and outputs matrixelements of the selected weight pattern to weight multipliers 420-0through 420-M and 430-0 through 430-M.

Specifically, if bit count≦length switch timing information 1, matrixelements of weight pattern 2016 conforming to a parity check matrix withmemory length M1=3 are output to weight multipliers 420-0 through 420-Mand 430-0 through 430-M.

If bit count>memory length switch timing information I and bitcount≦memory length switch timing information 2, matrix elements ofweight pattern 2017 conforming to a parity check matrix with memorylength M2=5 are output to weight multipliers 420-0 through 420-M and430-0 through 430-M.

And if bit count>memory length switch timing information 2, matrixelements of weight pattern 2016 conforming to a parity check matrix withmemory length M1=3 are output to weight multipliers 420-0 through 420-Mand 430-0 through 430-M.

In this way, a memory length relating to encoding of the front part andrear part of a transmission information sequence can be made smaller,and as a result, the number of initial states and end states of anencoder can be reduced.

As described above, according to this embodiment, weight control section2010 stores weight patterns 2016 and 2017 conforming to parity checkmatrices with different memory lengths, and when input bits are aninformation sequence, a weight pattern with a short memory length isused in the front part and rear part of the information sequence. Sincethe number of initial states and end states of an encoder can be reducedas memory length M decreases, the amount of computation and processingdelay time associated with encoding/decoding can be reduced.

In this embodiment, a case has been described by way of example in whichencoding is performed using memory length M1=3 in the front part andrear part of a transmission information sequence, and using memorylength M2=5 in other parts, but this is not a limitation, and an effectof reducing the number of initial states and end states of an encodercan still be obtained by the present invention if a parity check matrixfor which memory length M1 used in the front part and rear part of atransmission information sequence is set to an arbitrary memory lengthof less than 3, or for which an amount of decrease from memory length M2to memory length M1 is made arbitrary, is used.

(Embodiment 9)

In this embodiment, a description is given of a configuration of anLDPC-CC encoder that is designed so that, in encoding of an LDPC-CCcomprising a plurality of polynomials, encoding processing is startedusing a polynomial for which the memory length is minimum among theplurality of polynomials, and encoding processing is ended using apolynomial for which the memory length is minimum among the plurality ofpolynomials. Use of such a configuration enables the number of states ofan encoder at the start and end of encoding to be reduced, enabling theamount of computation and processing delay time associated withencoding/decoding to be reduced.

FIG. 37 shows parity check matrix 2100 according to this embodiment.Parity check matrix 2100 is a parity check matrix for which the numberof polynomials is 2—that is, a parity check matrix that defines atime-varying-period-2 LDPC-CC. Each row of parity check matrix 2100corresponds to a check polynomial, and each column corresponds to acodeword bit. The two polynomials are given by Equation (7-1) andEquation (7-2).

[7](D ¹⁶ +D ¹⁰ +D ⁶+1)X(D)+(D ¹⁷ +D ⁸ +D ⁴+1)P(D)=0 . . .   (Equation 7-1)(D ¹⁷ +D ⁸ +D ⁴+1)X(D)+(D ¹⁹ +D ¹² +D ⁵+1)P(D)=0 . . .   (Equation 7-2)

Below, a first polynomial given by Equation (7-1) is referred to aspolynomial p1, and a second polynomial given by Equation (7-2) isreferred to as polynomial p2.

The memory lengths of first polynomial p1 are Md1=16 and Mp1=17, wheresubscripts d and p indicate information bits and parity bits. The memorylengths of second polynomial p2 are Md2=17 and Mp2=19. That is to say,of first polynomial p1 and second polynomial p2, both memory lengths areshorter for first polynomial p1.

As stated in Embodiment 8, the shorter the memory length, the smaller isthe number of encoder states, and therefore, in order to reduce thenumber of states, it is desirable for encoding to be started using apolynomial for which the memory length is short, and for encoding to beended using a polynomial for which the memory length is short.

At this time, by starting encoding with first polynomial p1, encodingcan be performed using a polynomial for which the memory length is shortat the start of encoding. On the other hand, when the time-varyingperiod is 2, and two polynomials are used alternately, a polynomial atthe end of encoding varies according to the number of information bitsthat are encoded. Consequently, encoding processing cannot necessarilybe ended using a polynomial for which the memory length is short.

Thus, in this embodiment, polynomial adjustment section 2210 isprovided, and provision is made for encoding always to be ended with apolynomial for which the memory length is short.

FIG. 38 shows a main configuration of a transmitting apparatus accordingto this embodiment. As compared with transmitting apparatus 1000 in FIG.14, transmitting apparatus 2200 in FIG. 38 employs a configuration thatadditionally includes polynomial adjustment section 2210.

Polynomial adjustment section 2210 finds number of adjustment bits Nadjusing number of transmission information bits Ndata and number ofLDPC-CC polynomials Npoly.

FIG. 39 shows a configuration of polynomial adjustment section 2210.Polynomial adjustment section 2210 is equipped withnumber-of-adjustment-bits calculation section 2211, known bit generationsection 2212, and known bit adding section 2213.

Here, LDPC-CC encoding section 1010 starts LDPC-CC encoding usingpolynomial p1 for which the memory length is minimum.

Therefore, if an index of an information bit to be encoded is designatedNi (=1, 2, . . . , Ndata), an information bit having an index satisfyingthe equation Ni%Npoly=1 is encoded using polynomial p1. Here, “%”represents an operator that finds a remainder of a division.

From number of transmission information bits Ndata and number ofpolynomials Npoly, number-of-adjustment-bits calculation section 2211finds the minimum number of adjustment bits Nadj for which(Ndata+Nadj)%Npoly=1, and outputs the obtained number of adjustment bitsNadj to known bit generation section 2212.

Known bit generation section 2212 generates a number of known bitsequivalent to number of adjustment bits Nadj. Any bit sequence can beused as known bits as long as it is a bit sequence known on thetransceiver side and on the receiver side. For example, an all-zerosequence or the like can be used as known bits equal in number to Nadj.Known bit generation section 2212 sends the generated known bits toknown bit adding section 2213.

Known bit adding section 2213 adds the known bits equal in number toNadj to the rear part of a transmission information hit sequence, andsends this to LDPC-CC encoding section 1010.

Thus, in this embodiment, encoding can be started and ended dependablyusing polynomial p1 for which the memory length is minimum by havingpolynomial adjustment section 2210 insert known adjustment bits.

Number-of-adjustment-bits calculation section 2211 sends number ofadjustment bits Nadj to control information generation section 1050. Bythis means, Nadj is transmitted included in control information,enabling Nadj to be conveyed to the receiver side. Information conveyedto the receiver side need not be Nadj, but may be only informationnecessary for Nadj to be calculated on the receiver side, and may beNdata%Npoly, or the number of transmission information bits and thenumber of polynomials, for example.

In this embodiment, a case has been described in which the number ofpolynomials is two—that is, the time-varying period is 2—but this is nota limitation, and application is also possible in a similar way when thenumber of polynomials is three or more.

In this embodiment, a case has been described by way of example in whichthere is only one polynomial for which the memory length is minimum, butthere may also be a plurality of polynomials for which the memory lengthis minimum. For example, if the total number of polynomials is five, andmemory lengths Mp1 through Mp5 are set as MP1=16, MP2=18, MP3=16,MP4=20, and MP5=19, polynomial p1 is used when Ni%Npoly=1 and polynomialp3 is used when Ni%Npoly=3, and therefore provision may be made forpolynomial adjustment section 2210 to find the minimum Nadj for which(Ndata+Nadj)%Npoly=1 or 3.

Also, a case has been described in which polynomial adjustment section2210 according to this embodiment makes a polynomial used at the startand end of encoding a polynomial for which the memory length is short byadding known bits to the rear part of a transmission informationsequence, but the configuration and operation of polynomial adjustmentsection 2210 are not limited to this case.

FIG. 40 shows another sample configuration of polynomial adjustmentsection 2210. Polynomial adjustment section 2210 in FIG. 40 is equippedwith remainder calculation section 2214 and polynomial directive signalgeneration section 2215.

From number of transmission information bits Ndata and number ofpolynomials Npoly, remainder calculation section 2214 calculatesremainder Nrem given by Nrem=(Ndata)%Npoly. Remainder calculationsection 2214 sends generated remainder Nrem to polynomial directivesignal generation section 2215.

Polynomial directive signal generation section 2215 generates apolynomial directive signal from remainder Nrem. The polynomialdirective signal is generated as described below. Consider, for example,a case in which Npoly=2. When the two polynomials, polynomial p1 andpolynomial p2, are as shown in Equation (7-1) and Equation (7-2), thememory length is shorter for first polynomial p1, and therefore LDPC-CCencoder 1010 starts encoding using polynomial p1.

Therefore, when Nrem=1, the Ndata'th transmission information bit isencoded using polynomial p1. On the other hand, when Nrem=0, theNdata'th transmission information bit is encoded using polynomial p2.

If encoding is performed using a polynomial for which the memory lengthis short at the end of encoding as well as at the start of encoding, thenumber of states can be reduced. Consequently, when Nrem=1, polynomialdirective signal generation section 2215 outputs a directive signal toLDPC-CC encoder 1010 for the last bit to be encoded using polynomial p1for which the memory length is short.

Since LDPC-CC encoder 1010 starts encoding using polynomial p1 andthereafter performs encoding while switching polynomials, if Nrem=1 forthe last bit, encoding is performed on the last bit using polynomial p1even if there is no directive signal. Consequently, provision may bemade for polynomial directive signal generation section 2215 not tooutput a directive signal.

On the other hand, if Nrem=0 for the last bit, encoding is performedusing polynomial p2 for which the memory length is long. Consequently,in order to avoid this, polynomial directive signal generation section2215 outputs a directive signal to LDPC-CC encoder 1010 for the last bitto be encoded using polynomial p1. As a result, the order in whichpolynomials are used for LDPC-CC encoding is “p1, p2, p1, p2, p1, p2,p1, p1”.

In this way, polynomial adjustment section 2210 can give a directive sothat LDPC-CC encoder 1010 always uses a polynomial for which the memorylength is short for encoding of the last bit, enabling the number ofstates at the start and end of encoding to be reduced, and enabling theamount of computation and processing delay time necessary forencoding/decoding to be reduced.

In the above description, a ease has been described in which thetime-varying period is 2—that is, the number of polynomials is two—butthis is not a limitation, and application is also possible in a similarway when the number of polynomials is three or more.

Also, in the above description a case has been described by way ofexample in which there is one polynomial that gives a minimum memorylength, but this is not a limitation, and the number of polynomials thatgive a minimum memory length may also be two or more. In this case,polynomial directive signal generation section 2215 generates apolynomial directive signal so that encoding ends with one of thepolynomials that gives a minimum memory length, and sends this signal toLDPC-CC encoder 1010.

(Embodiment 10)

In this embodiment, a decoder is described that decodes an LDPC-CCcodeword encoded by switching among a plurality of weight patternsdescribed in Embodiment 1. Below, a case in which an LDPC-CC codewordencoded by switching among a plurality of weight patterns conforming tothe parity check matrix shown in FIG. 5 will be described as an example.

FIG. 41 shows a main configuration of a receiving apparatus according tothis embodiment. Configuration parts in receiving apparatus 2300 in FIG.41 that are identical to those of receiving apparatus 1200 in FIG. 17are assigned the same reference numbers as in FIG. 17, and descriptionsthereof are omitted here. Receiving apparatus 2300 in FIG. 41 mainlycomprises receiving antenna 1201, radio section 1202, quadraturedemodulation section 1203, channel fluctuation estimation section 1204,control information detection section 1205, logarithmic likelihoodcomputation section 1206, deinterleaving section 1207, and sum-productdecoding section 2310.

Sum-product decoding section 2310 has a received logarithmic likelihoodratio sent from deinterleaving section 1207 and a transmissioninformation sequence length sent from control information detectionsection 1205 as input, performs sum-product decoding, and obtains adecoded result.

FIG. 42 shows the configuration of sum-product decoding section 2310.Sum-product decoding section 2310 is equipped with storage section 2311,row processing computation section 2312, column processing computationsection 2313, and switching section 2314. Storage section 2311, rowprocessing computation section 2312, and column processing computationsection 2313 form matrix processing computation section 2315.

Storage section 2311 stores external value α_(mn), obtained by rowprocessing and a priori value β_(mn) obtained by column processing.

Row processing computation section 2312 reads a necessary a priori valueβ_(mn) from storage section 2311, and performs row processingcomputation in accordance with a parity check matrix H row-directionweight pattern. The weight pattern is switched based on switching timinginformation. In row processing computation, row processing computationsection 2312 performs decoding of a single parity check code using apriori value and obtains external value α_(mn).

Processing of the m'th row will now be described.

External value α_(mn) is updated using update equation (8) below for allpairs (m,n) satisfying the equation H_(m,n)=1.

$\begin{matrix}\left( {{Equation}\mspace{14mu} 8} \right) & \; \\{\alpha_{mn} = {\left( {\prod\limits_{n^{\prime} \in {{A{(m)}}\backslash\; n}}\;{{sign}\mspace{11mu}\left( \beta_{{mn}^{\prime}} \right)}} \right){\Phi\left( {\sum\limits_{n^{\prime} \in {{A{(m)}}\backslash\; n}}{\Phi\left( {\beta_{{mn}^{\prime}}} \right)}} \right)}}} & \lbrack 8\rbrack\end{matrix}$

Here, Φ(x) is called a Gallager f function, and is defined by thefollowing equation.

$\begin{matrix}\left( {{Equation}\mspace{14mu} 9} \right) & \; \\{{\Phi(x)} = {\ln\frac{{\exp(x)} + 1}{{\exp(x)} - 1}}} & \lbrack 9\rbrack\end{matrix}$

Column processing computation section 2313 reads a necessary externalvalue α_(mn), from storage section 2311, and performs column processingcomputation in accordance with a parity check matrix H column-directionweight pattern. The weight pattern is switched based on switching timinginformation.

In column processing computation, column processing computation section2313 performs the decoding of repetition code using input logarithmiclikelihood ratio λ_(n) and external value α_(mn), and finds a priorivalue β_(mn).

Processing of the n′th column will now be described.

β_(mn) is updated using update equation (10) below for all pairs (m,n)satisfying the equation H_(mn)=1. Only when the calculation is performedwith α_(mn)=0.

$\begin{matrix}\left( {{Equation}\mspace{14mu} 10} \right) & \; \\{\mspace{2mu}{\beta_{mn} = {\lambda_{n} + {\sum\limits_{m^{\prime} \in {{B{(n)}}/\; m}}\alpha_{m^{\prime}n}}}}} & \lbrack 10\rbrack\end{matrix}$

Switching section 2314 switches the weight patterns of row processingcomputation section 2312 and column processing computation section 2313based on weight pattern switching timing. Weight pattern switchingtiming may be input from outside, or may be generated within switchingsection 2314. FIG. 42 shows a configuration in which switching section2314 has a received logarithmic likelihood ratio and transmissioninformation sequence length n as input, performs received logarithmiclikelihood ratio counting, and calculates weight pattern switchingtiming using that count value and transmission information sequencelength n.

FIG. 43 shows the configuration of row processing computation section2312. Row processing computation section 2312 is equipped with selectors2312-1 and 2312-2, first computation section 2312-3, and secondcomputation section 2312-4.

Selectors 2312-1 and 2312-2 switch the transmission destination of an apriori value and the reception destination of an external value based onswitching timing information.

First computation section 2312-3 performs row processing computationbased on weight pattern 475. Weight pattern 475 is a pattern provided inweight pattern storage section 472 of weight control section 470. Secondcomputation section 2312-4 performs row processing computation based onweight pattern 476. Weight pattern 476 is a pattern provided in weightpattern storage section 473 of weight control section 470.

FIG. 44 shows the configuration of column processing computation section2313. Column processing computation section 2313 is equipped withselectors 2313-1 and 2313-2, first computation section 2313-3, andsecond computation section 2313-4. Selectors 2313-1 and 2313-2 switchthe transmission destination of an a priori value and the receptiondestination of an external value based on switching timing information.

First computation section 2313-3 performs column processing computationbased on weight pattern 2313-5, and second computation section 2313-4performs column processing computation based on weight pattern 2313-6.Weight pattern 2313-5 and weight pattern 2313-6 are weight patternsconforming to the parity check matrix in FIG. 5 stored by weight controlsection 470 on the encoding side.

When received logarithmic likelihood ratio count value C<2n, switchingsection 2314 generates switching timing information directing thatweight pattern 475 is to be used; when 2n+1≦C<2(n+5), switching section2314 generates switching timing information directing that weightpattern 476 is to be used; and in case of 2n+11≦C or above, switchingsection 2314 generates switching timing information directing thatweight pattern 475 is to be used.

Also, when received logarithmic likelihood ratio count value C<2(n−5),switching section 2314 generates switching timing information directingthat weight pattern 2313-5 is to be used; when 2(n−1)≦C<2n, switchingsection 2314 generates switching timing information directing thatweight pattern 2313-6 is to be used; and when 2≦C, switching section2314 generates switching timing information directing that weightpattern 2313-5 is to be used.

Switching section 2314 outputs switching timing information generated inthis way to row processing computation section 2312 and columnprocessing computation section 2313. By this means, row processingcomputation section 2312 and column processing computation section 2313can execute decoding processing conforming to an LDPC-CC parity checkmatrix used on the encoding side.

After repeating row processing and column processing a predeterminednumber of times, sum-product decoding section 2310 obtains an aposteriori logarithmic likelihood ratio.

As described above, a receiving apparatus according to this embodimentis equipped with sum-product decoding section 2310, and sum-productdecoding section 2310 is configured so as to switch weight patterns usedin row processing computation and column processing computationaccording to switching timing information. In this way, it is possibleto implement sum-product decoding of a codeword encoded by switchingweight patterns as described in Embodiment I.

In this embodiment, an LDPC-CC defined by the parity check matrix shownin FIG. 5 has been described, but this is not a limitation, and anLDPC-CC with a different memory length and different weight patterns,for example, may also be used.

In this embodiment, a receiving apparatus and decoder have beendescribed that correspond to the encoder in Embodiment 1, but this isnot a limitation, and by changing switching timing information andweight patterns to correspond to the encoder in Embodiment 2, forexample, a receiving apparatus and decoder that correspond to theencoder described in Embodiment 2 can be configured.

The present invention is not limited to the above-described embodiments,and various variations and modifications may be possible withoutdeparting from the scope of the present invention. For example, in theabove embodiments, cases have mainly been described in which the presentinvention is implemented by an encoder and transmitting apparatus, butthe present invention is not limited to this, and can also beimplemented by means of a power line communication apparatus.

It is also possible for the encoding method and transmitting method tobe implemented by software. For example, provision may be made for aprogram that executes the above-described encoding method andcommunication method to be stored in ROM (Read Only Memory) beforehand,and for this program to be run by a CPU (Central Processing Unit).

Provision may also be made for a program that executes theabove-described encoding method and transmission method to be stored ina computer-readable storage medium, for the program stored in thestorage medium to be recorded in RAM (Random Access Memory) of acomputer, and for the computer to be operated in accordance with thatprogram.

It goes without saying that the present invention is not limited toradio communication, and is also useful for power line communication(PLC), visible light communication, and optical communication.

One aspect of an LDPC-CC encoder of the present invention employs aconfiguration having: a plurality of shift registers; a plurality ofweight multiplication sections that multiply outputs of the shiftregisters by a weight; a modulo 2 adder that performs modulo 2 additionof outputs of the plurality of weight multiplication sections; a bitcounter that counts a number of input bits that are encoded; and aweight control section that controls weights of the plurality of weightmultiplication sections according to the number of bits.

According to this configuration, LDPC-CC encoding that uses a paritycheck matrix can be performed.

One aspect of an LDPC-CC encoder of the present invention employs aconfiguration in which the weight control section stores a first weightpattern conforming to a parity check matrix and a second weight patternconforming to a parity check matrix obtained by deforming the paritycheck matrix, and uses the first weight pattern when the input bits arean information sequence, and uses the second weight pattern when theinput bits are a termination sequence.

According to this configuration, a shift register weight value can beswitched according to whether input bits are an information sequence ora termination sequence. Therefore, the LDPC-CC encoder can concludetermination processing by means of setting a weight values by which atransmission codeword sequence is multiplied to be 0 irrespective of thevalue of the transmission codeword sequence when input bits are atermination sequence. As a result of this, the LDPC-CC encoder canreduce the length of the transmitted termination sequence because.

One aspect of an LDPC-CC encoder of the present invention employs aconfiguration in which the second weight pattern is a weight patternconforming to a parity check matrix in which a rightmost 1 of each rowof the parity check matrix has been changed to a 0.

According to this configuration, when input bits are a terminationsequence the LDPC-CC encoder can set a weight value by which atransmission codeword sequence is multiplied to be 0 irrespective of thevalue of the transmission codeword sequence. As a result, the length ofa transmitted termination sequence can be reduced.

One aspect of an LDPC-CC encoder of the present invention employs aconfiguration in which the second weight pattern is a weight patternconforming to a parity check matrix obtained by left-shifting arightmost 1 of each row of the parity check matrix to a column not usedfor a termination sequence parity check.

According to this configuration, in termination sequence decoding,encoding gain due to repetition code in sum-product decoding can bemaintained since the number of row-direction 1s (row weight) does notchange.

One aspect of an LDPC-CC encoder of the present invention employs aconfiguration in which the second weight pattern is a weight patternconforming to a parity check matrix obtained by left-shifting the samenumber of rightmost 1s of each row of the parity check matrix for eachrow.

According to this configuration, fewer kinds of weight patterns arestored.

One aspect of an LDPC-CC encoder of the present invention employs aconfiguration in which the second weight pattern is a weight patternconforming to a parity check matrix obtained by changing a 1 of a rowcorresponding to a check bit to a 0 in the parity check matrix.

According to this configuration, the LDPC-CC encoder can set a weightvalue by which a transmission codeword sequence is multiplied to be 0irrespective of the value of the transmission codeword sequence, and alength of a transmitted termination sequence can be greatly reduced.

One aspect of an LDPC-CC encoder of the present invention employs aconfiguration further equipped with a puncturing section that, when theinput bits are a termination sequence, punctures a systematic bit of thetermination sequence.

According to this configuration, if a termination sequence is made azero sequence that is known on the receiver side, for example, adecrease in transmission efficiency can be suppressed by puncturing thatzero sequence.

One aspect of an LDPC-CC encoder of the present invention employs aconfiguration in which the weight control section stores a plurality ofweight patterns conforming to parity check matrices having differentmemory lengths, and when the input bits are an information sequence,uses a weight pattern with a shorter memory length toward the rear ofthe information sequence.

According to this configuration, the memory length is made shortertoward the rear of an information sequence, enabling the terminationsequence length to be made shorter, and enabling degradation oftransmission efficiency to be suppressed.

One aspect of an LDPC-CC encoder of the present invention employs aconfiguration in which the weight control section stores a plurality ofweight patterns conforming to parity check matrices having differentcoding rates, and when the input bits are an information sequence, usesa weight pattern with a lower coding rate toward the rear of theinformation sequence.

According to this configuration, the coding rate is made lower towardthe rear of an information sequence, enabling error resilience intermination processing to be strengthened even if a termination sequenceis reduced.

One aspect of a transmitting apparatus of the present invention employsa configuration having: an LDPC-CC encoding section that executesLDPC-CC encoding on input bits; and a termination sequence puncturingsection that punctures a termination sequence included in a sequenceafter LDPC-CC encoding.

According to this configuration, the termination sequence transmissionamount can be reduced and a decrease in transmission efficiency can besuppressed.

One aspect of a transmitting apparatus of the present invention employsa configuration in which the termination sequence puncturing sectionincreases the proportion of punctured bits toward the rear of atermination sequence.

According to this configuration, a rear part of a termination sequencehaving relatively little effect on a transmission codeword sequence canbe punctured preferentially in termination processing, enabling thetermination sequence transmission amount to be reduced while suppressingdegradation of the error rate characteristic of a received informationsequence.

One aspect of a transmitting apparatus of the present invention employsa configuration in which the termination sequence punctures the entiretermination sequence.

According to this configuration, if a termination sequence is known onboth the transceiver side and the receiver side, the terminationsequence transmission amount can be greatly reduced.

One aspect of a transmitting apparatus of the present invention employsa configuration further equipped with a first buffer that stores atermination sequence punctured by the termination sequence puncturingsection, wherein a termination sequence stored in the first buffer istransmitted when a retransmission request is sent from a communicatingparty.

According to this configuration, if a position at which an error hasbeen detected is identified as a termination sequence position by anLDPC-CC parity check, it is possible to retransmit only a puncturedtermination sequence, enabling a decrease in transmission efficiency dueto retransmission to be suppressed.

One aspect of a transmitting apparatus of the present invention employsa configuration further equipped with a second buffer that stores theinput bits before the LDPC-CC encoding section.

According to this configuration, in the event of a retransmissionrequest, LDPC-CC encoding can be executed using a different coding ratewith high error correction capability on the same transmissioninformation sequence, and the proportion of bits received correctly canbe increased.

One aspect of a transmitting apparatus of the present invention employsa configuration in which the second buffer rearranges the order of theinput bits in order from the rear.

According to this configuration, by storing input bits with their orderrearranged, transmission is performed in a retransmission using adifferent sequence order from that used in an initial transmission,enabling the proportion of bits affected by an error in an initialtransmission that are incorrect again to be reduced.

One aspect of a transmitting apparatus of the present invention employsa configuration in which the second buffer rearranges the order of theinput bits in order from the rear.

According to this configuration, a rearward bit that is likely to beaffected by an error in an initial transmission is LDPC-CC encoded in afront part in a retransmission, enabling the probability of the same bitbeing incorrect in a retransmission to be reduced.

One aspect of a transmitting apparatus of the present invention employsa configuration further equipped with: an information sequence divisionsection that acquires first and second sequences by dividing aninformation sequence into two; an outer encoding section that encodesthe second information sequence; and a rearranging section thatrearranges the order of the first information sequence and the secondinformation sequence that has undergone outer encoding; wherein theLDPC-CC encoding section executes LDPC-CC encoding on output bits fromthe rearranging section.

According to this configuration, when two sequences are acquired bydividing an information sequence into a front part and rear part, outerencoding can be executed on a rearward information sequence likely to beaffected by an error in termination, and therefore if an error occurs inthe rear part of a received information sequence, that error can becorrected, and degradation of reception quality can be suppressed.

One aspect of a transmitting apparatus of the present invention employsa configuration in which the outer encoding section performs low-densityparity-check block code (LDPC-BC) encoding.

According to this configuration, high error correction capability can beachieved while reducing the circuit scale used for outer encoding.

One aspect of a transmitting apparatus of the present invention employsa configuration in which the rearranging section rearranges the firstinformation sequence and the second information sequence that hasundergone encoding so that a parity sequence obtained by the outerencoding section is positioned forward preferentially.

According to this configuration, part of an outer codeword sequenceobtained by outer encoding can be preferentially positioned toward thefront of a transmission information sequence, enabling the encoding gainof outer encoding to be improved.

One aspect of a transmitting apparatus of the present invention employsa configuration having: an LDPC-CC encoding section that executesLDPC-CC encoding on input bits and generates transmission codeword bits;and a puncturing section that punctures the transmission codeword bitsusing a first puncture pattern, and a second puncture pattern wherebymore bits are punctured than with the first puncture pattern, for eachprocessing unit of the transmission codeword bits.

One aspect of a transmitting apparatus of the present invention employsa configuration in which the puncturing section uses the first puncturepattern at the start of a processing unit of the transmission codewordbits.

According to these configurations, the number of rows that exert anadverse effect in a parity check matrix used in BP decoding on thereceiver side (decoding side) can be reduced, enabling degradation ofreception quality to be suppressed.

One aspect of a transmitting apparatus of the present invention employsa configuration in which the puncturing section uses the first puncturepattern at the rear of a processing unit of the transmission codewordbits.

According to this configuration, rows of a parity check matrix for whichreliability is propagated are included both forward and rearward in a BPdecoding processing period, and therefore reliability can be propagatedefficiently.

One aspect of a transmitting apparatus of the present invention employsa configuration in which the puncturing section allocates the firstpuncture pattern and the second puncture pattern to a processing unit ofthe transmission codeword bits, based on timings of a BP (BeliefPropagation) decoding processing unit time on the receiver side and aprocessing unit of the transmission codeword bits, in such a way that aplurality of the transmission codeword bits used by the first puncturepattern are included in the BP decoding processing unit time.

According to this configuration, the range within which decoding can beperformed by a row of a parity check matrix for which reliability ispropagated in a BP decoding processing period input signal increased,enabling reliability to be propagated efficiently.

One aspect of an LDPC-CC encoder of the present invention employs aconfiguration in which the weight control section stores a plurality ofweight patterns conforming to parity check matrices having differentmemory lengths, and uses a weight pattern with a shorter memory lengthfor encoding toward the front part of the input bits and the rear partof the input bits.

One aspect of an LDPC-CC encoder of the present invention employs aconfiguration in which the weight control section stores a plurality ofweight patterns conforming to a plurality of polynomials, and uses aweight pattern conforming to a polynomial for which the memory length isminimum among the plurality of polynomials for encoding of the first bitof the input bits, and uses a weight pattern conforming to a polynomialfor which the memory length is minimum among the plurality ofpolynomials for encoding of the last bit of the input bits.

One aspect of an LDPC-CC encoder of the present invention employs aconfiguration further equipped with a known bit adding section that addsa number of known bits corresponding to the number of input bits and thenumber of polynomials to the rear part of the input bits.

One aspect of an LDPC-CC encoder of the present invention employs aconfiguration in which the weight control section uses a weight patternconforming to a parity check matrix for which the memory length isminimum among the plurality of polynomials for encoding of the last bitof the input bits.

According to these configurations, the number of states at the start andend of LDPC-CC encoding can be reduced, and the amount of computationand processing delay time necessary for encoding/decoding can bereduced.

One aspect of an LDPC-CC decoder of the present invention is an LDPC-CCdecoder that decodes a Low-Density Parity-Check Convolutional Code(LDPC-CC), and employs a configuration having: a matrix computingelement equipped with a plurality of weight patterns conforming to aparity check matrix; and a switching section that switches among theplurality of weight patterns based on weight pattern switching timing.

According to this configuration, an LDPC-CC codeword encoded using aparity check matrix can be decoded using that parity check matrix.

One aspect of an LDPC-CC decoder of the present invention employs aconfiguration in which the switching section has a weight switchingtiming calculation section that counts the number of receivedlogarithmic likelihood ratios, and calculates weight pattern switchingtiming using that count value and a transmission information sequencelength.

According to this configuration, even in a case in which a parity checkmatrix weight pattern is switched, an LDPC-CC codeword can be decodedusing the relevant parity check matrix.

The disclosures of Japanese Patent Application No. 2007-183492, filed onJul. 12, 2007, Japanese Patent Application No. 2007-339913, filed onDec. 28, 2007, and Japanese Patent Application No. 2008-178241, filed onJul. 8, 2008, including the specifications, drawings and abstracts, areincorporated herein by reference in their entirety.

Industrial Applicability

A low density parity check convolutional code (LDPC-CC) encoder andtransmitting apparatus according to the present invention can performerror correction encoding/decoding while reducing the amount of atermination sequence necessary for LDPC-CC encoding/decoding andsuppressing degradation of transmission efficiency, and are useful foran LDPC-CC encoder that executes error correction encoding using LDPC-CCencoding, an LDPC-CC decoder, and so forth.

The invention claimed is:
 1. A Low-Density Parity-Check ConvolutionalCode (LDDC-CC) encoder comprising: a plurality of shift registers; aplurality of weight multipliers that multiply outputs of the shiftregisters by a weight; an exclusive OR computing circuit that finds anexclusive OR of outputs of the plurality of weight multipliers; a bitcounter that counts a number of input bits that are encoded; and aweight controller that controls weights of the plurality of weightmultipliers according to the number of bits, wherein: the plurality ofshift registers includes a shift register for information sequence and ashift register for parity; the shift register for parity inputs anoutput from the exclusive OR computing circuit; and the weightcontroller stores a first weight pattern conforming to a parity checkmatrix of a LDPC-CC and a second weight pattern conforming to a deformedparity check matrix obtained by deforming the parity check matrix of theLDPC-CC, and uses the first weight pattern when an information sequenceof the input bits is input into an earliest shift register of the shiftregister for information sequence, and uses the second weight patternwhen a predetermined input termination sequence for creating an encodedtermination sequence is input into an earliest shift register of theshift register for information sequence.
 2. The LDPC-CC encoderaccording to claim 1, wherein the deformed parity check matrix isobtained by left-shifting a rightmost 1 of each row of the parity checkmatrix of a LDPC-CC to a column not used for a termination sequenceparity check.
 3. The LDPC-CC encoder according to claim 1, wherein thedeformed parity check matrix is obtained by changing a 1 in rowscorresponding to a parity bit to a 0 in the parity check matrix of theLDPC-CC.
 4. The LDPC-CC encoder according to claim 1, further comprisinga puncturer that, when the input bits are the input terminationsequence, punctures a systematic bit of the encoded terminationsequence.
 5. The LDPC-CC encoder according to claim 1, wherein theweight controller stores a plurality of weight patterns conforming toparity check matrices having different memory lengths, and when theinput bits are an information sequence, uses a weight pattern with ashorter memory length toward a rear part of the information sequence. 6.The LDPC-CC encoder according to claim 1, wherein the weight controllerstores a plurality of weight patterns conforming to parity checkmatrices having different coding rates, and when the input bits are aninformation sequence, uses a weight pattern with a lower coding ratetoward a rear part of the information sequence.
 7. The LDPC-CC encoderaccording to claim 1, wherein the weight controller stores a pluralityof weight patterns conforming to parity check matrices having differentmemory lengths, and uses a weight pattern with a shorter memory lengthfor encoding toward a front part of the input bits and a rear part ofthe input bits.
 8. The LDPC-CC encoder according to claim 1, wherein theweight controller stores a plurality of weight patterns conforming to aplurality of polynomials, and uses a weight pattern conforming to apolynomial for which memory length is minimum among the plurality ofpolynomials for encoding of a first bit of the input bits, and uses aweight pattern conforming to a polynomial for which memory length isminimum among the plurality of polynomials for encoding of a last bit ofthe input bits.
 9. The LDPC-CC encoder according to claim 8, furthercomprising a known bit adder that adds a number of known bitscorresponding to a number of the input bits and a number of thepolynomials to a rear part of the input bits.
 10. The LDPC-CC encoderaccording to claim 8, wherein the weight controller uses a weightpattern conforming to a parity check matrix for which memory length isminimum among the plurality of polynomials for encoding of a last bit ofthe input bits.